FETCH - DECODE - EXECUTE CYCLE

Question 1

What happens during the fetch stage?

Answer 1

• The address stored in the Program Counter (PC) is copied to the Memory Address Register (MAR). The MAR holds the address of the memory location from which the instruction will be fetched.
• The instruction stored at the address in the MAR is retrieved from memory and copied into the Memory Data Register (MDR) via the data bus. The CU generates control signals to manage this data transfer, ensuring that the correct read operation is performed.
• Simultaneously, the PC is incremented by 1 to point to the address of the next instruction in the sequence. The CU activates this increment operation, preparing the CPU for the next fetch.
• The value held in the MDR (the fetched instruction) is then copied to the Current Instruction Register (CIR). The CU controls this transfer as well.

Question 2

What happens during the decode stage?

Answer 2

• The contents of the CIR are decoded. This involves separating the instruction into two parts:
  
  • Opcode: Specifies what operation the CPU needs to perform (e.g., add, subtract).
  • Operand: Identifies the data or memory locations needed for the operation.
• The CU interprets the opcode and operand. It determines the necessary actions based on the instruction and generates appropriate control signals for execution.
• If additional data is needed, it is fetched from memory and passed to ACC

Question 3

What happens during the execute stage?

Answer 3

• The CPU executes the decoded instruction
• The CU directs the Arithmetic Logic Unit (ALU) to perform arithmetic or logical operations if the instruction requires it, managing the necessary
  data paths through control signals. Results from calculations are copied to the ACC
• If the instruction involves moving data, the CU controls the data flow between registers and memory, ensuring that the correct data is read from or written to the appropriate locations.