Fe-de-ex Cycle

Question 1

Steps in Fetch part

Answer 1

PC is checked, since it contains the address of the next instruction to be executed.

The addressed store is copied into the MAR.

Address is sent along an address bus to main memory, where it waits to receive a signal from control bus.

To read this data, control unit sends a “read” signal along control bus to main memory.

Contents stored in memory can now be sent along the data bus to MDR.

Data received by MDR from memory now gets copied into CIR.

Question 2

State the Decode part

Answer 2

Instruction held in CIR is decoded by the decode unit, which contains an opcode and an operand.

We need to load contents of memory location x into CPU’s ACC.

Question 3

State the Execute part

Answer 3

The instruction is executed, using the ALU if necessary. Sometimes, this stage requires loading or saving data to and from the main memory

Address gets sent down through the address bus to main memory.

Control unit sends a “read” signal through the control bus to main memory.

Contents stored at an address can now be sent along the data bus to the MDR.

Contents of MDR are copied to ACC. Instruction complete.