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Microprocessors > Examen 1 > Flashcards

Examen 1 Flashcards

1
Q

Bit

A

A variable which can only assume two values, 0 or 1.

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2
Q

Nibble

A

4-bit word

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3
Q

Byte

A

8-bit word

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4
Q

Word

A

16-bit word

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5
Q

Double Word

A

32-bit word

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6
Q

Quad

A

64-bit word

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7
Q

Least Significant Bit

A

Rightmost bit

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8
Q

Most Significant Bit

A

Leftmost bit

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9
Q

How many different word can be formed with n-bits

A

2^n different words

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10
Q

Kilo(K)

A

1k = 2^10

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11
Q

Mega(M)

A

1M = 2^20

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12
Q

Giga(G)

A

1G = 2^30

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13
Q

Tera(T)

A

1T = 2^40

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14
Q

How to convert from Base R to Decimal

A

Expansion Method

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15
Q

How to convert from Decimal to Base R

A

Use division method for integer part and multiplication method for fractional part

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16
Q

Division Method

A

Divide the number to be converted by the desired base the remainder is your a0 and the quotient is for repeating the process you stop when quotient is 0.

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17
Q

Multiplication Method

A

Multiply by the desired base the integer part is your a-1 the fractional part is for repeating the process you stop when a zero decimal part is reached, to decimal parts are the same or you exceeded 8 multiplications.

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18
Q

How to convert Octal and Binary

A

Associate each octal digit to three binary digits and viceversa

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19
Q

How to convert HEX and Binary

A

Associate each hex digit to four binary digits and viceversa

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20
Q

What is the word size of a register

A

quantity of bits in each location its determined by the data bus size

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21
Q

How do you determine the number of locations of a memory

A

2^address lines

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22
Q

Mention Memory Types

A

RAM,ROM,PROM,EPROM,EEPROM

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23
Q

Microprocessor Unit

A

Contains a general purpose CPU,Buses,memory,and I/O interfaces. They are optimized to move code and data from external memory into the chip

24
Q

Micro-controller Unit

A

Less complex CPU. CPU,Memory & I/O are integrated within a single chip. They are more application oriented than general purpose microprocessor.

25
Q

Describe the CISC Arquitecture

A

-Variable length instructions
-Large instruction set
-Focuses in accomplishing as much as possible with each instructions.
Hardware complex programming easier.

26
Q

Describe the RISC Arquitecture

A

-Fixed length instructions
-Short instruction set
-Focuses on simple instructions
Hardware simplified and programming harder

27
Q

Components of a CPU Arquitecture

A
  • ALU
  • Control Unit
  • Registers
  • Bus Interface Logic
28
Q

Datapath

A

Collection of hardware components within the CPU performing data operations.

29
Q

Controlpath

A

Hardware components performing system control operations

30
Q

What is the ALU

A

Performs supported logic and arithmetic operations

31
Q

What is the BIL

A

The CPU structures that coordinate the interaction between the internal buses and the system buses

32
Q

Whats is a Register

A

A temporary storage for data, memory addresses, and control information in a way that can be easily accessed.

33
Q

Mention and Describe the Special Purpose Registers

A

IR(Instruction Register) - holds the instructions that is beign currently decoded and executed in the CPU
PC(Program Counter) - holds the address of the instruction to be fetched from memory by the CPU.
SP(Stack Pointer) - refers to top of the stack.
SR(Status Register) - contains flags.

34
Q

Mention and Describe the flags in the Status Register

A

ZF(Zero Flag) - result of an operation is 0.
CF(Carry Flag) - set when an operation produces a carry
NF(Negative Flag) - set when result of an operation is negative and cleared otherwise

35
Q

Mention and Describe the flags in the Status Register

A

ZF(Zero Flag) - result of an operation is 0.
CF(Carry Flag) - set when an operation produces a carry
NF(Negative Flag) - set when result of an operation is negative and cleared otherwise
VF(Overflow Flag) - signals an overflow on addition or subtraction cleared otherwise.
IF(Interrupt Flag) - indicates whether a program can be interrupted by an external event or not

36
Q

What is an Address Bus

A

A set of lines transporting address information.They are unidirectional.

37
Q

What is a Control Bus

A

Group of all the lines carrying the signals that regulate the system activity. They are unidirectional.

38
Q

High Bank

A

Odd Addresses

39
Q

Low Bank

A

Even Addresses

40
Q

Big Endian

A

Data is stored with the most significant byte in the lowest address and the least significant byte in the highest address

41
Q

Little Endian

A

Data is stored with the least significant byte in the lowest address and the most significant byte in the highest address

42
Q

Memory Map

A

Model representation of the usage given to the addressable space of a microprocessor based system

43
Q

Global Memory Map

A

Depicts the entire addressable space

44
Q

Partial Map

A

Provides detail of only a portion of addressable space

45
Q

What is the I/O subsystem composed of?

A

All the devices (peripherals) connected to the system buses

46
Q

Input Transaction

A

Moves information into the CPU from a peripheral device

47
Q

Output Transaction

A

Send information out from the CPU to external devices

48
Q

Mention the common peripherals to be found in most embedded systems

A

Timers, Watchdog Timer, Communication interfaces, Analog-to-Digital Converter, Digital-to-Analog Converter, Development peripherals

49
Q

Timers

A

These peripherals can be programmed for any use of prescribing time intervals

50
Q

Watchdog Timer

A

Used as a safety device. It resets if it does not receive a signal generated by the program every X time units

51
Q

Communication Interfaces

A

Used to exchange information with another IC or system

52
Q

Development Peripherals

A

Download the program into the MCU and for debugging

53
Q

I/O Mapped I/O

A

Have separate address spaces for memory and I/O devices, requiring specific input and output instructions

54
Q

Memory Mapped I/O

A

I/O devices are inside the memory space

55
Q

Control Registers

A

Allow for configuring the operation of the device and the interface itself.Also called Mode or Configuration Register

56
Q

Status Register

A

Allow for inquiring about the device and interface status

57
Q

Data Register

A

Allow for exchanging data with the device itself

Microprocessors (1 decks)

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