Exam Prep Flashcards
Fill in the Blank: EIA-232 (a.k.a. RS-232) wad originally developed to interface computing equipment known as ______________________ with local ____________________________
Data Terminal Equipment (DTE), Data Communication Equipment (DCE)
What was Data Communication Equipment (DCE) used for?
Modulating and demodulating analog signals (modems)
What are the TXD and RXD line in the EIA-232 standard?
TXD: Data transmission line from DTE to DCE
RXD: Data transmission line from DCE to DTE
Define Universal Synchronous Asynchronous Receiver Transmitter (UART)
A hardware module to implement serial communication according to various standards, including RS232
How does a UART system function?
A Data Rec. line is either polled or triggers an interrupt when a character is received. Then, a Tx Rdy line (either polled or triggers an interrupt) indicates whether a transmit buffer is empty and a new character can be written/transmitted
What is a baud rate?
It defines how many signal changes occur per second
True or False: In EIA-232, the idle state of RXD/TXD lines are logic low. The transmitting device will pull the line high for the duration of one bit
False, idle state of RXD/TXD lines are logic high and the transmitting device pulls the line low for the duration of one bit
True or False: A receiving device that is activated in UART initiates a bit timer that operates at a frequency 16x, 32x, or 64x the baud rate
True
Fill in the Blank: UART registers occupy ___ contiguous addresses
8
Define a Line Control Register (R/W) in UART
A register used at initialization to set the communication parameters
True or False: The last bit in the Line Control Register (LCR) controls access to DLL and DLM registers
True. These registers are mapped to the same address as RBR (receive), THR (transmit), and IER (interrupt) registers
Define Divisor Latch Registers (R/W)
Registers that contain the least and most significant bytes of a divisor to generate the time base of (1.8432MHz / 16) / DLR
Define Serial Communications Interface (SCI)
An asynchronous serial communication system, similar to RS-232. It operates at TTL voltage level (0V=Low, 5V=High) and uses an 8- or 9-bit data frame. SCI hardware includes two 10- or 11-bit shift registers and two Serial Communication Data Registers (SCDR) (one read, one write)
How does an SCI system transfer data?
Data is written to the SCDR buffer (8 bits) and is copied to 10- or 11-bit transmit shift registers and the T8 (for 9-bit frame), start, and stop bits are added.
After this, the frame is shifted out 1 bit at a time specified by the baud rate register. Once the data is transferred from the buffer to the shift register, a TDRE (Transmit Data Register Empty) flag is set (or triggers an interrupt)
True or False: Unlike RS-232, SCI clocks are only 4x faster than its baud rate
False, SCI clocks are similar to RS-232 and are 16x faster than its baud rate (meaning SCI hardware counts 16 times between changes to TxD output line)
Explain how an asynchronous receiver accepts data
The start bit triggers the receiver to shift in the next 10 (or 11) bits at the set baud rate. The start and stop bits are removed and 8 bits of data are loaded to the SCDR (for a 9-bit frame, R8 is also loaded).
Following this, the Receive Data Register Full (RDRF) flag is set when new data is available in SCDR. Reading the data will reset the flag
Define Serial Peripheral Interface (SPI)
A synchronous communication protocol (devices operate from the same clock) that operates on a master-slave relationship. SPI defines communication lines, the clock used, and does not include flow control or acknowledge mechanisms. It can also be implemented on any physical channel (TTL, RS-232, RS-422, etc.)
What are the two data lines and two control lines that SPI uses
Master Output Slave Input (MOSI): Data line driven by master and received by slave
Master Input Slave Output (MISO): Data line driven by slave(s) and received by master
Clock Signal (SCK): Control line generated by the master (50% of duty cycle)
Slave Select Line (SS): Control line for selecting multiple slaves (optional)
Explain how a Serial Peripheral Interface (SPI) transmits data
An 8-bit data register (SPDR) in the master device and an 8-bit data register in slave (also SPDR) are linked (using two 8-bit SPSRs) as a 16-bit register.
During data transfer, the 16-bit register is shifted 8 bits by the SCLK. Data written to the SPDR of the master are transmitted to the slave, and vice versa.
The transmitting devices uses one edge of the clock to change the output and the receiving devices uses the other edge to accept the data.
Explain how SPI timing operates
There are three bits, MSTR, CPOL, and CPHA, in the control register that determine the master device and the active edge of the clock (master and slave both must be configured with the same set of parameters). If MSTR=1, it generates SCK, else, SCK is an input.
CPOL and CPHA determine polarity and phase. If CPHA=0, device will shift in the data on 1st, 3rd, 5th, … clock edge. Else, it will shift on 2nd, 4th, 6th, … clock edge.
If CPOL=CPHA, data is shifted on rising edge. Else, it is shifted on falling edge
