Exam 3 - BK Flashcards
What are the two digital logic states?
Logic 1 (ON)
Logic 0 (OFF)
How many bits in a Byte?
8
How many bits is a Nibble?
4
What are the two advantages of Digital signals?
- Error detection and correction (MOST IMPORTANT)
- Stored memory in semiconductors
What does ADC stand for
Analogue to Digital
What does DAC stand for
Digital to Analogue
List 2 common ADC circuits
- Successive Approximation Register (SAR)
- Dual Slope
What is the basic operation of an ADC
Converts an analogue signal voltage to a string of binary code depending on the value of the analogue input voltage
If the inputs to an AND gate are 1 & 0, what is the output
0
If the inputs to an OR gate are 1&1, what is the output
1
How many inputs and outputs are there in a NOT gate
1 Input, 1 Output
What is another name for a NOT gate?
Inverter
On a XOR gate, when the input is 1&1, what is the output
0
What is Fan-In
The number of inputs a logic gate can accept
What is Fan-Out
The number of inputs a logic gate can drive
What must be used if a logic gate has a High Fan-In of more than 10 inputs
A buffer
What is the disadvantage of a High Fan-In logic gate
Slower due to its complexity
What is the normal Fan-out output of any logic gate, and how can it be expanded?
Normal Fan-Out = 10
Can be expanded with a buffer
What is propagation delay?
Time required for a digital signal to travel from input to output
What problems does propagation delay cause in an asynchronous circuit?
Intermittent faults
Does propagation delay increase or decrease with temperature
Increase
Does propagation delay increase or decrease with output load increase
Increase
In a logic circuit, what are some advantages in keeping the number of components to a minimum?
- Keep costs low
- Reduce complexity
- Reduce size of power supply
- Reduce propagation delay
What is the most basic flip-flop that all other bi-stable latches and multi-vibrators are made from?
SR Flip Flop
(Set-Reset)
What does the term “Transparent” mean when talking about flip-flops?
Output responds immediately to input
Are SR Flip-Flops Synchronous or Asynchronous?
Asynchronous
How many inputs and outputs does and SR Flip-Flop have?
2 Inputs (Set-Reset)
2 outputs (Q - notQ)
Which 3 ways can the clock signal be read?
Edge Trigger:
-Positive Edge (Rising)
-Negative Edge (Falling)
Level Trigger:
- When clock pulse reaches a certain logic level (Usually 1)
How is a Gated SR Flip-Flop different from a standard SR Flip-Flop?
A clock signal input
How many inputs in a Gated SR Flip-Flop?
3 Inputs:
-Set
-Reset
-Clock (Enable) Input
What is the disadvantage to a Gated SR Flip-Flop that is fixed by adding inputs ‘Preset and Clear’
Uncertainty in switching
What is a disadvantage to a Gated SR Flip-Flop w/Preset&Clear that is fixed by using a D-type Flip-Flop?
Using a D-type Flip-Flop eliminates need for having 2 additional input for Preset and Clear by connecting an inverter between Set and Reset (or between J and K)
How many inputs to a D-type Flip-Flop?
2 Inputs:
Clock and ‘D’ input
How is a Master-Slave Flip-Flop constructed?
2 bi-stable SR circuits connected in a cascade
How does a T-Type Flip-Flop work?
Output changes state every application of a clock signal and latches onto that signal until another input signal is added
What can the T-type Flip-Flop also be used for?
Frequency Divider - Output frequency is half of input frequency
In a JK Flip-Flop, what happens when both J and K are 1
Q toggles
What does Clear and Preset do?
Cleared to 0 or Preset to 1 independently of clock signal
Is D-type transparent?
Yes
Where is the inverter placed in a data flip flop?
In-between S and R inputs
What are some uses for T-type?
Frequency Divider
Binary Counter
Is T-type commercially available?
No, can be made by connecting the J and K inputs together
What output condition must be avoided in a SR Flip-Flop?
S=0
R=0
- Invalid Output
What Flip-Flop was made to overcome the S=R=0 condition in a SR Flip-Flop?
JK Flip Flop
(Added clock signal)
What are the 4 outputs conditions of a JK Flip-Flop?
Logic 1
Logic 0
No Change
Toggle
What does the JK Flip-Flop suffer from?
It suffers from the timing problem dubbed ‘Race’
How is ‘Race’ in a JK Flip-Flop overcome
By keeping the timing pulse as short as possible by reducing the period.
This is done by increasing frequency.
What Flip-Flop is used to eliminate timing problems in a JK Flip-Flop?
Master-Slave Flip-Flop
Where does the Master circuit trigger on the clock pulse?
Triggers on positive edge of clock pulse
When does the Slave circuit trigger on the clock pulse?
Triggers on the negative edge
Where does the feedback go to on a Master-Slave circuit?
The output of the Slave circuit is fed back to the Master circuit
Is the Master-Slave Flip-Flop Synchronous or Asynchronous?
Synchronous
What is the most common use for a Square Wave?
Clock and Timing Signal
What is the duty cycle of a square wave?
50% duty cycle
What is the equation for finding the frequency of a square wave?
Frequency = 1 / (ON time + OFF time)
Is a rectangular wave symetrical?
No nigga
What is another name for the Positive and Negative wave half on a rectangular wave?
Mark and Space
