Exam 2 Review - Pipelining Flashcards
(T/F) Pipelining improves performance by making individual instructions execute faster
False: The instructions themselves do not execute faster but the throughput of the system increases
(T/F) A control hazard occurs when an instruction cannot execute because data that it is dependent on is not available yet
False: The description above is for a data hazard. A control hazard occurs when the proper instruction cannot execute in the right cycle because the instruction fetched was not the correct one. These occur with branch instructions, like cbnz.
(T/F) A structural hazard could occur if we only had one memory for both program instructions and data
False: With only one memory, we would not be able to fetch an instruction and load data into a register in the same cycle.
(T/F) A load-use hazard requires a stall before the load instruction, even with forwarding
False: The stall must be after the load because unlike other instructions where the result comes out of the ALU in the third stage, the result here comes out of data memory in the fourth stage.
What is the purpose of the forwarding unit in the hardware?
The forwarding unit helps prevent certain stalls from data hazards by sending the result of an operation immediately to a previous stage and avoiding having to wait until the write-back stage.
In the slides and book we used terms like IF/ID, ID/EX, MEM/WB, etc. What exactly is meant by those terms?
X/Y refers to the buffers in the current stage of the pipeline. The first value is the buffer we are reading from. the second value is the buffer we are writing to. For example, in ID/EX we are reading the data from the instruction decode buffer and writing it to the execution buffer.
Given our five-stage pipeline and n number of instructions, write a formula for calculating how many cycles it would take to finish all the instructions if there were no hazards.
The first instruction takes 5 cycles. Every instruction after adds an addition cycle if there were no hazards. A formula for n instructions then might be
5 + n – 1 cycles
(With forwarding) identify any potential hazards in the rightmost column. How many cycles do the instructions take to finish?
11 total cycles 5 cycles for the first instruction, 1 cycle for other 5 instructions, and 1 cycle for the load-use hazard.
List some of the strategies we can implement to deal with control hazards.
Static Prediction: Assume that the branch is always/never taken. Only take branches backward/forward
Dynamic Prediction: Use bits to try and predict whether we should branch or not (1-bit or 2-bit predictors). If the MSB is a 1, then we predict a branch, else we do not. We update the values of the bit(s) depending on if the prediction was correct or incorrect.
Branch Delay Slot: Re-order the instructions so that the instruction immediately following the branch is not dependent on the branch
List and describe the three hazards we are concerned with in Pipelining.
Structural - Multiple functions try to access the same memory in the same cycle
Let’s say we have a 2-bit predictor. Our 2-bit predictor starts out at 00 and we enter a for-loop that runs 12 times. What is the prediction accuracy for this branch?
