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0447 Comp. Org. & Assembly > Exam 2 > Flashcards

Exam 2 Flashcards

1
Q

ISA

A

Specifies the software interface to the CPU
(Instructional Set Architecture)

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2
Q

Microarchitecture

A
  • hardware design of a physical CPU
  • an implementation of an ISA
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3
Q

Control

A

Tells everything else what to do and when
- decode the instruction and set all the control signals to make that instruction happen
- automatically sets the control signals to the right values to make each instruction happen

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4
Q

Registers

A
  • Hold the values being computed
  • temporary stopping point for your program’s data
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5
Q

ALU

A

Computes new values from old values
Arithmetic and Logic Unit

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6
Q

Values move between what

A

Registers and ALU

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7
Q

Architectural Registers

A
  • registers that the ISA specifies
  • GPR < Architectural < Microarchitectural
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8
Q

GPR

A

registers you can use for any purpose in programs
- General Purpose Registers

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9
Q

Microarchitectural registers

A
  • exist outside the ISA and are part of the implementation of the CPU
  • used for temp storage, implement multistep operations, control specific features, etc.
  • Often inaccessible from software
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10
Q

Register File

A
  • Holds General-purpose registers
  • like an array of registers or small word addressed memory
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11
Q

PC register

A
  • part of the control
  • says what step to do next
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12
Q

PC

A

memory address (send it to memory)
- memory sends back data (instruction) and the control decodes the instructions and tells things what to do
Program Counter

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13
Q

CPU’s Job

A

to read and execute instructions
(Fetch, Decode, Execute (Once per instruction))

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14
Q

Fetch

A

gets the next instruction to execute from memory by using PC
- Instruction memory

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15
Q

Decode

A

Control reads the instruction
- look at the fetched instruction and set control signals
Control/Register File

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16
Q

Executes

A

The control does the instruction by telling other parts what to do
- wait for data to flow through the ALU
ALU

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17
Q

how many times is memory accessed for a load or store?

A

-1st access: to fetch instruction
-2nd access: to actually load the value

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18
Q

Schematic

A

Graphical way to represent systems (flowcharts)

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19
Q

HDL

A

Hardware Description Languages (text)

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20
Q

EDA

A

Electronic design automation (schematics)

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21
Q

Schematics and texts are…

A

equal in power

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22
Q

Circuit schematics show…

A

how data flows from one component to another

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23
Q

components can

A

produce or consume values (or both)

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24
Q

Is there order in circuit schematics?

A

NO
everything in the circuit happens simultaneously

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25
Q

Boolean Function

A

takes one or more Boolean (t/f) inputs and produces a Boolean output

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26
Q

truth table

A

summarizes a Boolean function by listing the output for every possible combination of inputs

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27
Q

gate

A

implements one of the basic Boolean logic functions

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28
Q

What can all computation be built from

A

All computation can be built from just the basic Boolean logic operations (AND, OR, and NOT)

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29
Q

Add two three-bit numbers

A
  • need three one bit adders
  • chain the carries from each place to the next higher place
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30
Q

Propagation Delay

A

every gate and wire has it
- the amount of time needed for a signal to “propagate” through it

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31
Q

ripple carry

A

linear in the number of bits
- if you double number of bits, double the amount of time needed

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32
Q

overflow

A

Get a number too big to be represented and it gets wrapped around

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33
Q

If you add two n-digit numbers in any base…

A

the result will have at most n + 1 digits

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34
Q

3 options to deal with overflow

A
  1. store
  2. ignore
  3. fall on the floor (crash)
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35
Q

Ignore option

A
  • worst and most common way to respond to overflow
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36
Q

Crash option

A
  • better than ignoring
  • generates CPU Exception (can be detected and handled)
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37
Q

Arbitrary Precision Arithmetic

A

two 8-bit adds, starting with LSB
- the carry bit from the first add is carried into the second add
- can keep chaining them together

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38
Q

overflow in unsigned addition

A

in unsigned addition, if the MSB has a carry out of 1, an overflow happened

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39
Q

overflow in signed addition

A

in signed addition, overflow occurs if we add two numbers of the same sign and get the opposite sign

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40
Q

signed subtraction

A

same as signed addition, apply the rule after doing the negation

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41
Q

overflow for unsigned subtraction

A

overflow occurs when the MSB’s carry out is 0 not 1

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42
Q

overflow for signed subtraction

A

same as addition, but check after negating second input

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43
Q

two paths can be done…

A

at the same time

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44
Q

when making a decision in hardware you…

A

do all possible things, then pick only the thing you need, and ignore the rest

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45
Q

Multiplexer

A

(mux)
- outputs one of its inputs based on t=a select input

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46
Q

Demultiplexer

A

(Demux)
- opposite of multiplexer
(with very few exceptions, you won’t need these)

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47
Q

negate means

A

change the sign to the opposite

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48
Q

shifting left by n is the same as…

A

multiplying by 2^n

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49
Q

shifting right by n is the same as…

A

dividing by 2^n

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50
Q

Arithmetic Right Shift

A

used for signed numbers
- “smears” the sign bit into the top bits
(pushes 1s in the left place while scooting right)

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51
Q

And

A

intersection
set of things that are in both sets

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52
Q

Or

A

Union
the set of things that are in either set

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53
Q

XOR

A

Symmetric set difference
set of items in one set but not both

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54
Q

Mask

A

specifically constructed value that has 1s in the bits it wants to keep and 0s in the bits that we want to discard

(&<bitwise> 000001111, 1s being the bits we want to keep) (same is doing 1st number mod 16)</bitwise>

55
Q

To isolate the lowest n bits,

A

And with 2^n-1 or bits & ((1 < < n) - 1

56
Q

no finite number of fractional places can

A

represent infinite fractions, because writing infinite fractional places would require infinite storage

57
Q

how are floats represented

A

as a fixed-length binary number with fractional places

58
Q

every operation on floats round

A

the result off to the nearest representable float
- (a + b) + c may not be equal to a + (b + c)

59
Q

floats don’t use what?

A

2’s complement
(they use sign magnitude)

60
Q

Combinational Logic

A

you give it some combo of inputs and you get an output

61
Q

one kind of memory

A

a circuit that remembers information and memory is the basis of sequential circuits due to propagation delay

62
Q

sequential circuits

A

can perform sequences of operations

63
Q

clock signal

A

says when we move to the next step

64
Q

clock edges

A

when it changes between 1 and 0
rising and falling edges

65
Q

clock cycle

A

time from one rising edge to another rising edge

66
Q

write enable

A

like a door on the input of the register

67
Q

when the write enable is 0

A

it ignores the clock and the value never changes
chooses if we change a register’s value on each cycle

68
Q

state

A

all the things remembered by the system

69
Q

blinky states

A

on or off

70
Q

state transition table

A

sequential version of a truth table
encodes the same information as a state transition diagram

71
Q

FSM

A

Finite State Machine
way of thinking about a sequential process where there is state (memory), the state changes based on the current state transition logic and (optionally) inputs, there are outputs based on the states

72
Q

is multiplication slower than addition

A

yes

73
Q

when you multiply two n-digit/bit numbers

A

the product will be at most 2n digits/bits

74
Q

division

A

factoring polynomials
fundamentally slower

75
Q

how many addresses can you access in memory

A

You can only access one address in memory per clock cycle

76
Q

if you have one kind of resource and you want two users to use it, you have two options

A
  • make two instead of one so they can use them simultaneously
  • make the users take turns using one, over time
77
Q

Harvard Architecture

A

2 memories
- PC -> Instruction on memory -> instructions
- stores -> data memory -> loads
- easier for hardware designers

78
Q

Von Neumann

A

One memory (takes turns)
- PC, Stores -> Memory -> instructions, loads
- uses multiple clock cycles
- fetch instruction on first cycle
- perform variable load on second cycle (most common but more complex)
- easier for programmers

79
Q

Assemblers job

A

turns assembly language code (written by humans) into machine code (for the CPU to read) based on ISAW

80
Q

What makes instructions smaller

A

encoding instructions as bitfields

81
Q

jump

A

make execution go to one specific place
- absolute
- jumps (j, jal, jr) put a value (the jump target) into the PC

82
Q

branches

A

make execution go to one of two places
- relative

83
Q

absolute

A

sets the PC to a new value

84
Q

relative

A

it adds an offset to the current PC

85
Q

offset

A

destination - here (calc by assembler not CPU)

86
Q

FDXMW

A

Fetch, Decode, Execute, Memory Access, Write-back

87
Q

Memory Access

A

If its a load or store, do that
Data memory

88
Q

Write-back

A

If theres a destination register, write the result to it
Register File

89
Q

3 phases of decoding

A
  1. split the encoded bitfield into its constituent values
  2. from the opcode, determine which instruction we’re looking at
  3. map that instruction to a unique combination of control signals
    happens in control unit
90
Q

overall shape of control

A
  • the only input is current instruction, which gets split up
  • the opcode gets decoded to produce the instruction signals
  • the instruction signals are used to come up with the control signals
  • the outputs are some instruction fields and the control signals
91
Q

small numbers have

A

negative exponents

92
Q

large numbers have

A

positive exponents

93
Q

when you move the decimal to the left

A

you add to the exponent

94
Q

when you move the decimal to the right

A

you take away from the exponent

95
Q

(T)era

A

10^12

96
Q

(G)iga

A

10^9

97
Q

(M)ega

A

10^6

98
Q

(K)ilo

A

10^3

99
Q

(m)illi

A

10^-3

100
Q

micro (weird u)

A

10^-6

101
Q

(n)ano

A

10^-9

102
Q

(p)ico

A

10^-12

103
Q

Latency

A

how long a task takes to complete
- seconds per task

104
Q

Throughput

A

how many tasks you can complete in a span of time
- tasks per second

105
Q

improving latency

A

reducing amount of time that one task takes

106
Q

improving throughput

A

increasing the amount of work being done at once

107
Q

what is the best latency

A

shortest latency
(time/task)

108
Q

what is the best throughput

A

the one with the highest number of completed tasks
(tasks/time)

109
Q

making latency lower

A

can make throughput higher

110
Q

critical path

A

path through a circuit that requires the longest series of sequential operations

111
Q

fastest we can clock a sequential circuit

A

is the reciprocal of the critical path’s propagation delay

112
Q

problem with single cycle architecture

A
  • it ties the performance of the CPU to the performance of the RAM
  • clock cannot tick any faster than the instruction with the longest critical path
  • can’t run the clock any faster than memory latency
113
Q

what is the fastest a single cycle machine can run

A

66-83 MHz (66 to 83 million)
1 CPI

114
Q

pipeline registers

A

hold onto data for the next phase in multi cycle

115
Q

CPI

A

(Cycles Per Instruction)
- latency
- how many cycles it takes to complete one instruction
- lower is better (slower instructions take more cycles)
- Best is 1

116
Q

Total time

A

n * CPI * t seconds

117
Q

Microprogramming

A

Control is a FSM whose transition table is in a special memory

118
Q

microcode

A

(ucode)
small “programs” that encode the sequence of steps for each instruction

119
Q

sequencer

A

decides what steps to do next (control flow through uProgram)

120
Q

uInstruction

A

set of controls and FSM control flow information

121
Q

uCode ROM

A

(read only memory)
indexed by the uPC

122
Q

hardware control is faster

A

because it is smaller and simpler

123
Q

the longer the sequence of instructions gets

A

the closer the CPI

124
Q

the more stages instruction have

A

the higher the throughput gets

125
Q

cache

A

temporary holding area for recently used data
(memory references cache)

126
Q

temporal

A

these variables are used over and over, very quickly. It makes sense to keep them somewhere fast to access

127
Q

spatial

A

the items in this array are all next to each other in memory. the cache will pull in several items at a time

128
Q

scalar CPU

A

finish at most 1 instruction per cycle

129
Q

superscalar CPU

A

finishes more than one instruction per cycle

130
Q

pipelining

A

partially overlapping instruction execution to improve throughput and complete instructions faster

131
Q

Caching

A

keeping copies of recently used data in a smaller but faster memory so it can be accessed more quickly in the near future

132
Q

Out-of-Order

A

CPUs analyze several (a dozen or more) instructions in advance, then dynamically reorder them so they can be executed more quickly then they would as written

133
Q
A

0447 Comp. Org. & Assembly (2 decks)

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