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ENCE260 Flashcards

1
Q

CPU to Internal peripherals

A

control bus, data bus (double)

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2
Q

CPU to memory

A

control bus, address bus, data bus (double)

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3
Q

CPU key functions

A

arithmetic,
evaluate logic expressions,
determine and control program flow

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4
Q

expression for number of combinations in a sequence

A

M^n

M = number of combinations
n = number of digits

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5
Q

Word length

A

default number of bits manipulated by microcontroller
ATMega32u2 is 8bit

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6
Q

Two’s compliment

A

swap the bits and add 1
1 more negative than positive

eg: 111 is -1,
000 is always 000.

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7
Q

Floating point

A

31st bit MSB
S-E8-F23

1 = -, 0 = +, same as two’s
write the number as binary, keeping the dot
E = Add 127 to amount you moved dot
F = fractional - 2nds, 4ths, 8ths, 16ths, etc

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8
Q

Combinational logic

A

output is a function of input only

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9
Q

Sequential logic

A

combinational logic with memory

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10
Q

SR latch

A

2 Nor gates
R sets one Q to on and one to off, which stays,
S switches it and stays

Issues - don’t know what initial state will be
##########

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11
Q

D flip flop

A

SR latch that works with a clock signal

basically just add an and for data and clock (to S)
and a not with the other and (for R)

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12
Q

Register

A

D flip flops that share a clock signal and output to a data bus

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13
Q

Data bus

A

width equal to CPU word length
transports data to and from CPU

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14
Q

Address bus

A

specifies memory locations
address space is 2^buswidth
controlled by CPU

16 bit in ATMega32u2

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15
Q

Control bus

A

sends commands to hardware from the CPU

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16
Q

Von-Neumann/Princeton architecture

A

all memory is stored in one place. Loses efficiency, as you can process only one thing at once instead of 2

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17
Q

Harvard architecture

A

instruction and data memory separate

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18
Q

canonical form logical functions

A

logic functions made of just the three fundamental functions:
AND, OR, NOT

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19
Q

algebraic properties: closure

A

if a,b elements of B, any function involving a and b will be an element of B

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20
Q

algebraic properties: identity

A

a.1 = a, a+0 = a

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21
Q

algebraic properties: annihilation

A

a.0 = 0, a+1 = 1

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22
Q

algebraic properties: absorption

A

a+(a.b) = a
a.(a+b) = a

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23
Q

algebraic properties: Idempotence

A

a+a = a, a.a = a

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24
Q

algebraic properties: or-compliment

A

a+!a = 1

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25
Q

algebraic properties: and compliment

A

a.!a = 0

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26
Q

algebraic properties: De Morgan’s

A

!(a+b) = !a.!b
!(a.b) = !a+!b

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27
Q

Make the 3 fundamental functions out of NAND gates

A

!a = !(a.a)
a.a = !(!(a.a).!(a.a))
a+b = !(!a.!b)

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28
Q

minterm

A

the output of karnaugh maps
and of either notted or not notted variables, must have each variable present. combine these by cancelling individual notted and not notted variables

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29
Q

Karnaugh maps

A

used for logic circuit design.
rectangles must be 2^n by 2^m

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30
Q

sum of products SOP

A

summation of the minterms of a truth table

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31
Q

General purpose registers

A

IO register for ALU - increases speed - 32 registers in ATMega32u2

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32
Q

special/control registers

A

stores special variables that control overall behaviour

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33
Q

PC

A

program counter, part of the special/control registers.
stores address of the next instruction in program memory, controls/sets program flow

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34
Q

SP

A

stack pointer, part of the special/control registers.

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35
Q

Control/execute unit

A
  • fetches instructions from memory to the instruction register
  • decodes opcode
  • loads variables into GPR/SR and then controls loading them into the ALU.
  • Instructs the ALU what operations to execute and when.
  • stores output of the ALU into the correct GPR
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36
Q

Half adder

A

built from a left-right separation of a+b truth table
C - AND
S - XOR

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37
Q

full adder

A

two half adders combined.
The carry bits get ORed and outputted along with the sum. This makes the sum the 1’s column and the Carry the 2’s column

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38
Q

Decoder/Encoder

A

turns the bus’ n traces into 2^n outputs (decoder) and vice versa
works by breaking input into two traces, one with a not.
00 0001
01 0010
10 0100
11 1000

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39
Q

Priority encoder

A

only takes the highest 1 from the input

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40
Q

Multiplexer/demultiplexer

A

S chooses whether I0 or I1 is outputted (2:1 mux)
S needs to be sufficiently large to account for as many input options there are. generally 2^n = i

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41
Q

full adder subtraction

A

Goal is two’s compliment. Done by XOR with input line and a Sub line. The sub line goes in to the first carry to count as +1
You can use a truth table to confirm.

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42
Q

shift register

A

D flip-flops in series(Q -> D) with a common clock
Because change only occurs on the rising edge, the shift has to propagate through n rising edges before it stops

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43
Q

Ripple counter/timer

A

shift register where each !Q is connected back to D.
When rising edge detected, !Q goes high until another rising edge is detected. This doubles the time it takes to change for each flip flop along the register. When you take the output of this register, it appears to be counting up by 1 each rising clock edge.

note: count down by taking Q (instead of !Q) and applying XOR between the flip flops.

44
Q

propagation delay calculating

A

put n NOTs before an AND for one of the inputs. The resulting pulse of 1 will be n * propagation delay.

45
Q

Synchronous counter

A

built from ripple counter.
uses a common clock.
truth table for count states and next states shows what combinational logic needs adding.

Q0 -> !Q0 handled by !Q—D
Q1 -> Q1 XOR Q0
Q2 -> Q2 XOR (Q1.Q0)

all fed into respective D inputs.

46
Q

Finite state machine

A

initial state
inputs
transitions
outputs

47
Q

Moore FSM

A

Combinational logic based on input and current states determines states.
Feeds to combinational logic that performs tasks without further input

48
Q

Mealy FSM

A

Moore FSM with inputs also fed to the functional combinational logic

49
Q

tristate buffer

A

electronically controlled switch that boosts the power

50
Q

PINx output (GPIO)

A

Activated from the data bus going into the DDxn flip flop (set to 1). output is a tristate buffer (and pull-up resistor) control line that drives the PORTxn flip flop value to the pin

51
Q

PINx input (GPIO)

A

runs through a digitiser and sleep controller, then the PINxn register gets pushed by a tristate buffer to the data bus

52
Q

Pull-up resistor

A

only on when DDxn output is 0 (input state) and PORTxn output is 1 (active state).
Pulls up to high voltage to avoid floating pins. When the pin is grounded, current bypasses pin and input is 0. The resistor protects from the high voltage causing short circuit.

53
Q

MOSFET

A

Useful for controlling circuits with high voltages. The voltage runs perpendicular to the IO pin controlling it. Used in pull-up resistors.

54
Q

Watchdog timer

A

counts down and resets microcontroller if it reaches 0. Prevents loops.
Needs to be set to top periodically.

55
Q

ATMega32u2 timer functions

A

prescaler
capture
compare
PWM

56
Q

OCRnx

A

output compare register
n is the timer, 0 for 8bit, 1 for 16 bit.
x is the instance of the register (there are 3: A,B,C)

A defines the top point, the point where - when comparison matched - the counter counts down

57
Q

TCNTn

A

Timer counter
0 - 8bit
1 - 16bit

58
Q

OC.nx

A

Output channel for PWM (to pin)
based on duty cycle
n - TCNTn
x - instance of OCRnx

59
Q

PWM period

A

2*OCRnA/fclk

60
Q

duty cycle

A

% of time OC.nx is 1
OCRnx/OCRnA

61
Q

ADC

A

analogue digital conversion

sampling - discretise time
quantise - discretise voltage
encoding - represent as binary

62
Q

SREG

A

status register - in special registers

7: I Global interrupt enable/disable
6: T Transfer bit BLD, BST instructions
5: H Half carry flag
4: S N XOR V for signed tests
3: V Two’s compliment overflow flag
2: N negative from arithmetic logic
1: Z zero from arithmetic logic operation
0: C carry flag for arithmetic logic

63
Q

X, Y, Z in special registers

A

indirect address registers
X - 27 and 26
Y - 29 and 28
Z - 31 and 30
Stores addresses in GPR for faster access

64
Q

Opcode

A

Syntax | Operands | Operation
C registers | Opcode | Flags

adiw Rd+1:Rd, k |dom/range| Rd+1:Rd <- Rd+1:Rd + k
PC <- PC + 1 |Binary w/ vars| S,V,N,Z,C

65
Q

Setting a bit

A

PORTx|= (1«n);

66
Q

Clearing a bit

A

PORTx &= ~(1«n));

67
Q

Toggling a bit

A

PORTx ^= (1«n);

68
Q

test a bit

A

result = (PORTx & (1«n)) != 0;

69
Q

active high/low

A

on for high/low output voltage, respectively

70
Q

pull down resistor

A

goes to ground for active high circuits
eliminates floating pin.

71
Q

timer resolution

A

time between each increment
1/fclk

72
Q

max delay (timer)

A

T = 2^n * resolution

73
Q

ATMega32u2 prescaler usage

A

Timer counter control register
TCCR1B
(1 as in TCNT1)

(uses a mux internally, CSn0, CSn1, CSn3)
0: off
1: no prescaling
2: 8
3: 64
4: 256
5: 1024

74
Q

underflow

A

calculation is too close to 0 to be represented. common with integer division. eg: 10/5x10 (0) is not the same as 10x10/5 (20)

75
Q

LED matrix on/off

A

MOSFETS are closed when input is low. They have an inverse logic.

Both row and column therefore need to be low for the LEDs to be high->low

76
Q

Navswitch and LED combined functionality

A

both share the same pin. Because LED is active high and switch is active low, LED is on both when switch is off (pull-up resistor disconnected) and on (switch takes the pin to ground before the LED)

77
Q

paced loop overflow issue

A

going past the pacer period builds up after each iteration (assuming uniform function time) until there is an overflow of TCNTn itself, causing a really long pacer wait. This misses a whole cycle.

78
Q

Periodic scheduler

A

CPU sleeps when not time to execute. Paced loop is 100%.
TASK_RATE / x
if a task takes too long, can get timing jitter.

79
Q

task execution rate

A

for periodic scheduling
sum of function execution times/execution period

80
Q

half duplex

A

one at a time

81
Q

UART

A

universal asynchronous receiver/transmitter.
bit by bit.
Tx shift register -> Rx shift register for both. 2 wires.

82
Q

Baud rate

A

maximum number of bit transitions per second

83
Q

serial data transmission sequence

A

idle line - high
start bit - low
LSB first
data
parity bit
stop bit

84
Q

Parity bit

A

makes the whole transmission odd (odd parity bit)
eg: if data has 4 1s, parity will be 1 to make 5 total odd bits.

85
Q

USART registers on ATMega32u2

A

UCSR1A - control and status register
7: RXCn - receive complete
6: TXCn - Transmit complete - entire register shifted out
5: UDREn - data registry empty
UDR1 - Data register
Baud rate register

86
Q

IR modulation

A

done to distinguish from ambient light. done only on 0. TCNT0 used. 36khz common.

87
Q

C preprocessor

A

reads C source file, header files, expands macros. outputs .i

88
Q

C compiler

A

takes preprocessor output, checks for syntax errors, compiles to assembly. outputs .s

89
Q

C assembler

A

converts assembly to machine code, stored in binary. outputs .o

90
Q

loader

A

loads .out executable to .hex on the microcontroller

91
Q

makefile cryptic features

A

$^ -o $@
all prerequisites -o target - used for .out line
$< is first prerequisite, used for O file lines (first prereq is .C)

92
Q

Make clean

A

.PHONY: clean
clean:
-$(DEL) *.0 *.out *.hex

93
Q

git commands

A

add -> commit (-m message “message”) -> push (origin main)
<- pull/clone (origin main)
add -> commit
<- checkout HEAD
add
<- checkout
add -> commit
<- diff HEAD ->
add
<- diff ->

HEAD is most recent commit

94
Q

Encapsulation

A

putting related functions and data structures into its own module

95
Q

header file structure

A

ifndef “header_h”

#define “header_h”
#include “other_h”
functions
#endif

96
Q

Waterfall

A

specifications, design, implement, test/debug, maintenance

97
Q

Types of design methodology

A

top-down
bottom-up
hybrid

98
Q

coupling (design)

A

measure of modularity (how separate each module is)

99
Q

cohesion (design)

A

how related the functions are in each module

100
Q

Address bus width

A

log2(bits/8*words)
equivalent to
log2(memory byte count)

101
Q

Fetch

A

read PC from special register,
get function from program memory,
store opcode in instruction register

102
Q

Decode

A

interpret opcode
set up address busses, control lines (ALU), register address lines, all set up for I/O

103
Q

Execute

A

ALU performs operation using GPRs as I/O

104
Q

Special registers

A

Rd: Destination
Rr: Source
R: Result
K: Constant data
k: constant address
b: Bit in I/O register (3 bit)
s: Bit in status register (3 bit)
X,Y,Z: Indirect Address Registers
A: I/O location address
q: Displacement for direct addressing (6-bit)

105
Q

Classes of instruction

A

Data transfer
Arithmetic/logic
Branching (PC++, +-k)

106
Q

Phony target

A
107
Q
A

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