EE P3 Interview Technical Questions Flashcards
In digital timing analysis, what is SETUP TIME?
SETUP TIME is the amount of time that a data signal must be valid BEFORE the clock edge triggers the storage element.
In digital timing analysis, what is HOLD TIME?
HOLD TIME is the amount of time that a data signal must be valid AFTER the clock edge triggers the storage element.
In digital timing analysis, what is CLOCK SKEW?
CLOCK SKEW is the difference in arrival times of the clock signal at different points in a circuit.
What are differential pairs?
A pair of traces carrying equal and opposite signals for noise immunity and signal integrity.
Why is matching trace lengths important in differential pair routing?
To prevent timing skew and ensure both signals arrive at the receiver simultaneously.
What is the typical differential impedance for high-speed interfaces?
Usually 90Ω or 100Ω depending on the standard (e.g., USB, PCIe).
Why is impedance control important in high-speed design?
To prevent signal reflections and maintain signal integrity.
What factors affect trace impedance?
Trace width, trace thickness, distance from the ground plane, and the PCB material’s dielectric constant.
What is the typical single-ended impedance for a PCB trace?
Around 50Ω.
What is the purpose of termination in high-speed signals?
To match the impedance of the transmission line and prevent reflections.
What is series termination?
A resistor is placed in series near the driver to dampen reflections by matching the trace impedance.
What is parallel termination?
A resistor is placed at the receiver end between the signal and ground (or (V_{cc})) to absorb reflections.
What is crosstalk?
Unwanted interference between adjacent signal traces caused by electromagnetic coupling.
How can crosstalk be minimized?
Increase trace spacing, use ground planes, and consider routing sensitive signals on inner layers (stripline).
What is the difference between microstrip and stripline?
Microstrip: Trace on the outer layer with a ground plane beneath (higher crosstalk). Stripline: Trace sandwiched between two ground planes (lower crosstalk).
What is the primary concern with high-speed clock signals?
Ensuring minimal skew and maintaining signal integrity.
How can clock signal integrity be improved?
Use short, direct paths, and surround the clock trace with ground for isolation.
Why is a good PDN critical in high-speed design?
To ensure stable voltage levels and minimize noise.
How do decoupling capacitors help in a PDN?
They filter noise and provide local charge during transient events.
What is the role of power planes in a PDN?
Distribute power evenly and reduce impedance.
What is Thevenin termination?
A pair of resistors create a termination voltage by connecting to (V_{cc}) and ground.
What is AC termination?
A capacitor is placed in series with a termination resistor to block DC current and reduce power consumption.
Name a few tools used for signal integrity simulation.
HyperLynx, SIwave, ADS.
What type of simulation is SPICE typically used for?
Modeling transmission lines and termination effects.
