Digital IC Design

Question 1

What are some ways of storing information

Answer 1

Magnetic media - optical media - paper tapes - semiconductor memories

Question 2

What is a semiconductor

Answer 2

An electronic circuit that can store information

Question 3

Three types of Sequential access memory

Answer 3

Serial storage, FIFO, LIFO

Question 4

Types of ROM and what type is it?

Answer 4

Non volatile
ROM - Data built in fabrication
PROM - All data 1 with fuses that blow to crate 0 - can be written once

Question 5

Types of RWM/RAM?
And what type is it?

Answer 5

Voltatile
Static - basic cell is flip flop, low density but fast
Dynamic - Capacitor, high dencity but slow

Question 6

Cells equation:

Answer 6

1 Mbit = 2^20 cells -> 2^10 columns/rows

Question 7

EPROM?

Answer 7

Special transistors used at each row/column intersection. This transistor has 2 gates.
* When there is no initial charge in G2 and the voltage in G1 increases, voltage in G2
also increases due to capacitive effect. This effectively raises the threshold voltage of
the MOSFET but the channel can still be formed when G1=+5v.
* If G2 is negatively charged, no channel can be formed by G1=+5v anymore. Thus the
transistor remains permanently off as long as G2 is not discharged.
* G2 can be negatively charged by connecting G1 and DRAIN to +25v and the
SOURCE grounded. As G2 is surrounded by insulators, it will retain the charge for a
very long time.
* G2 can be discharged again by exposing it to ultraviolet light. UV generates electronhole pairs in SiO2 which allows the stored charges to leak off.
* Entire memory must be erased before reprogramming

Question 8

EEPROM?

Answer 8

Same as EPROM except that the insulator thickness is greatly reduced.
* When 20v is applied to G1 (control gate) while VD=0, electrons tunnel from n+
region to G2 (floating gate). This raises the threshold to 10v and the transistor
is effectively off.
* To discharge G2, zero volt is applied to G1 and 20v to VD.
* We may selectively erase blocks of EEPROM cells

Question 9

What’s an internal memory architecture?COPY TO OTHER FOLDER

Answer 9

Each cell stores one bit
Memory cells are arranged in an array format
The array is symmetric
By selecting appropriate row and column we can access any cell

Question 10

When is n N-Type mosftet produced and what is it’s structure?COPY TO OTHER FOLDER

Answer 10

N-type mosftet is produced when a bit of green NDiff track is crossed by a bit of red polysilicon - the NDiff is on either side of the polysilicon and froms the drain/souurce n+ for strongly doped with most electrons which reside in the two green NDiff tracks. The P substrate is lightly doped and made of a layer of silicon dioxide

Question 11

What are the two important dimensions of the N-channel mosfet?COPY TO OTHER FOLDER

Answer 11

Current flow from Drain -> Source -> Under gate(Red sili)
It is length L of the transistor and the width W across the gate to change performance you alter these values

Question 11

What happens if you connect one end of the n diff to ground and the other to a variable voltage VDS in a MOSFET?COPY TO OTHER FOLDER

Answer 11

We assume a small Vds of 1V and say that VGs = 0
The N-type in contact with the P-type form a diode from gate to source.
No current flows

Question 11

What happens once the layers are grown in the MOSFET?COPY TO OTHER FOLDER

Answer 11

Rest of polyslicon and oxide are etched away, the N type dopans are implanted in the regions either syde of the ply which become the N type, the bit bellow the red sylicon(gate) is protected so it’s not N type

Question 12

Summarise mosfets?COPY TO OTHER FOLDER

Answer 12

If the Vgs gate signal is above the voltage threshold Vt, the device is on and the current flows, otherwise it is off.
When the gate voltage VGs = 0 drain to channel is revsersed biased so there is no path from D to S
When Vgs > 0V and <vT electrons are repelled

Question 12

Equations for mosfet COPY TO OTHER FOLDER

Answer 12

Current is the rate of change of charge I = dQ/dT
so for a mosfter Ids = ChargeInChanel/TransitTime
TO GET TRANSIT TIME:
transitTime = Length/Velocity
Velocity = mobilty(u) * electricfield
Electricfield = VDs/L
So….
TRANSIT TIME = L^2/uVds
TO GET CHARGE IN CHANNEL:
Q = Cg *(VGS - Vchann - Vt)
Cg = eWL/D
so to bring it together
Ids = uew/LD[(VGS-VT)VDS - V^2ds/2]
OR
Ids = b[VGS-VT]Vds - V^Ds/2] (CCAN IGNORE vDS2/2 IF IT IS SMALL)

Question 12

What happens if you put a small voltage on the Gate in a mosfet?COPY TO OTHER FOLDER

Answer 12

The charge carriers that connected the source and the drain are repelled by the positive charge in the gate, thus the holes from the substrate and pushed away.
For a small voltage no current flows

Question 12

What happens if you put a big voltage on the gate of a MOSFET?COPY TO OTHER FOLDER

Answer 12

Strong electrical field due to the thin layer - strong field rips electrons out of the bonds in the source and drain.
Thus:
N-type drain with free electrons + source + the region in between.
Current flows!
The voltage for this to ocurr is usually denominated as vT

Question 12

What’s the proccess of transconduntence COPY TO OTHER FOLDER

Answer 12

K’ = ue/d - process of transconduntence, device transconductance = K’W/L

Question 12

How does a mosfet structure look like? COPY TO OTHER FOLDER

Answer 12

** -> gate
000 …..000-> n type s/d
……………………. -> p substrate

Question 12

What happens if VDS is to big in a mosfet COPY TO OTHER FOLDER

Answer 12

The voltage at the drain is 0 as a deplition region forms so max voltage you can have is when Vds = Vgs - Vt

Question 13

What is static ram

Answer 13

Static RAM (SRAM) is a type of random access memory(RAM) that
retains data bits in its memory as long as power is being supplied. for example cache memory

Question 14

What is a static ram cell?

Answer 14

A static RAM cell is a basic flip-flop
(e.g., two inverters connected back
to back)

Question 15

Difference between resist load SRAM and CMOS SRAM

Answer 15

Resistive Load SRAM :
* more compact cell size
* high standby current
CMOS SRAM:
* increased cell area
* low static power dissipation

Question 16

4 - transistor DRAM?

Answer 16

The parasitic capacitors will help maintain the transistor states.
* However, in a short while, the charge will leak and data will be lost.
* The memory must be refreshed repeatedly.
* Hence, it is called dynamic memory.

Question 17

SRAM vs DRAM

Answer 17

SRAM:
static RAM cell is designed by
cross-coupling the inputs and
outputs of two inverters.
▪ The data stored in the cell remains
stored as long a power is applied to
the cell.
▪ Usage of 4 to 6 transistors and
associated interconnections means
individual cells occupy a substantial
area and hence packing density is
low.
▪ Provides fast access time
DRAM:
▪ In dynamic RAM, a bit of data is
stored as a charge on a capacitor
where the presence or absence of
charge determines the value of
the stored bit.
▪ Since leakage current eventually
removes the stored charges,
DRAMs need to be refreshed at
regular intervals
▪ Any read operation also erases
the stored charge and therefore
must be followed by refresh
operation.
▪ Access time is higher
▪ Packing density is much higher
for DRAM

Question 18

Compare the decoders?

Answer 18

Bit-line decoder:
* Fast
* Needs more transistors
Tree decoder:
* m pass transistors cause longer delay
* Needs much fewer transistor
Compromised solution:
Using a combination of shallow, partial tree decoder
with smaller bit-line deocders.

Question 19

What are the type of interaction in a micro processor?

Answer 19

Synchronous : where sender and receiver access data according
to a reference clock.
or, Asynchronous : where there is no common clock signal.

Question 20

How does a synchronous data transfer work

Answer 20

• at point A when clock increment, begins a READ cycle.
• at point B, CPU generates the address
• at point C, the memory gives the data.
• at D, the CPU reads the data and ends the READ cycle.

Question 21

How does an asynchronous data transfer work

Answer 21

at point A, CPU generates the address.
* at point B, CPU asserts the Address strobe.
* at point C, the memory gives the data.
* at D, the memory informs the CPU that data is available.
* The CPU reads the data and then at E, negates the strobe.
* at F, the memory negates the Acknowledge signal.

Question 22

Memory merits and demerits of synchronous/asynchronous data transfer

Answer 22

Synchronous data transfer
* supports high data transfer rate
* needs a common clock signal
* the timing regime is very rigid
* all device must meet the same timing requirements
* the protocol is simple
Asynchronous data transfer
* does not depend on a common clock
* usually slower data transfer rate. Transfer usually occur at a rate
which is natural to the slave.
* more flexible, can utilise older (& slower) memory or I/O devices

Question 23

Control pins:

Answer 23

System Control group:
CLK – System Clock, between 8 to 16.67 MHz
RESET* – (as input) active low input forces 68000 into a known state. SP=[000000], PC=[000004].
(as output) When executed s/w RESET, it sends RESET* signal to all peripheral devices (68000’s
internal states are not affected).
HALT* – (as input) active low input stops the processor and negates all control signal. (as output)
68000 also assert HALT* to tell peripheral devices that an irrecoverable error has occurred.
Synchronous Bus control group:
E – provides a non-symmetric timing signal
VPA* – sent by peripheral to initiate synchronous data transfer.
VMA* – tells peripheral that address is on the bus.
Interrupt control group:
IPL0, IPL1, IPL2* – used by external devices to request service
Asynchronous Bus control group:
AS* – when asserted, indicates that a valid address is on the bus.
R/W – determines the nature of the memory access cycle
UDS* – indicates that the upper byte is to be accessed.
LDS* – indicates that the lower byte is to be accessed.
DTACK* – issued by the peripheral to denote that data bus are valid and 68000 may proceed.
BERR* – informs 68000 that an error has occurred in the current bus cycle.
Bus Arbitration group:
BR* – request for the control of bus by an alternative bus-master.
BG* – indicates that the bus-control has been granted.
BGACK* – the new bus-master asserts BGACK* responding to BG* and holds it low as long as it
uses the bus.
Function code group:
FC0, FC1, FC2 – denotes the current processor cycle and status

Question 24

Microcontroller vs microprocessor?

Answer 24

Micro controller:
At the heart of an embedded system, all peripherals are embedded into a single chip, circut can be simple and compact with low consumption and single voltage power rail is enough, uses flash memory to execute programs / can be used in compact system. Input and output is defined and the cost if low. Used for refrigirators and the such
Microprocessor:
At the heart of a comp sys all peripherals are connected externally and the circuit is connected and bulky, high consumption different power rai to be required - uses external ram and can not be used in a compact system hence not efficient. Cost of the system is higher and used in phones and such

Question 25

Full address decoding vs partial address decoding

Answer 25

Full address decoding
* All the higher address lines are used to specify a memory device
* Each physical memory location is identified by a unique address
* More hardware is required to design the decoding logic
* Higher cost for decoding circuit
* No multiple addresses
* Used in larger systems
Partial address decoding
* Since not all the address space is implemented, only a subset of the higher
address lines are needed to point to the physical memory device
* Each physical memory location is identified by several possible addresses (using
all combinations of the address lines that were not used)
* Hardware required to design decoding logic is less and sometimes can be
eliminated
* Less cost for decoding circuit
* It has an advantage of multiple addresses
* Used in small systems

Question 26

Advantages of uusing a prom as a logic device?

Answer 26

Advantages of PROM as a Logic Device are,
* As no minimization of logic circuits is needed the circuits can be designed easily.
* It is possible to modify the circuit faster.
* These are high speed as compared to discrete SSI/MSI circuits.
* The cost is lower.

Question 27

Using FPLA?

Answer 27

A programmable logic array (PLA) is a kind of programmable logic device to implement logic circuits.
* It has a set of AND gates, which link to a set of OR gates, which can then be conditionally inverted to produce an
output.
* Both the AND and the OR gate planes are programmable.
* It has 2N AND Gates for N inputs, and M OR Gates for M outputs,, each with programmable inputs. This layout
allows for many logic functions to be synthesized in the ‘sum of products’ forms.

Question 28

Using PAL?

Answer 28

PAL devices have arrays “fixed-OR, programmable-AND” plane to implement
“sum-of-products” logic equations for each of the outputs in terms of the inputs.