Data Types

Question 1

What are the basic verilog data types?

Answer 1

reg, wire, integer, real, time, realtime

Question 2

What are the four basic states of a verilog reg?

Answer 2

1,0,X,Z

Question 3

What new basic types does System Verilog add?

Answer 3

logic, bit, byte, shortint, int, longint, shortreal

Question 4

What is a structure?

Answer 4

A collection of data types that can be referenced via a common variable

Question 5

How is a structure declared?

Answer 5

typedef struct {
  int coins; real dollars;
} money;
money wallet;
wallet = '{5,19.75}; // '{default:0}; // '{coins:5, dollars:19.75};

Question 6

What is a fixed array?

Answer 6

A variable to store a basic data type in continuous locations

Question 7

How is an array declared?

Answer 7

int myFifo [0:7];
int myFifo [8];
int myArray [2][3];
bit [8*17:1] myMessage=”Hello World”;

Question 8

How to cast from an real to an int?

Answer 8

int’(2.0*3.0)
or system tasks
integer $rtoi(real)
real $itor(integer)

Question 9

What is the difference between reg and wire?

Answer 9

reg can only be driven in a procedural (always and initial) block and wire and only be used in an assign statement.

Question 10

What is the logic datatype?

Answer 10

It can be driven from procedural or assign but it can only have one driver, or a complier error. A net with more than one driver needs to be a wire.

Question 11

What is a bit?

Answer 11

Like logic but it only has two states: 0, 1

Question 12

What are the most common data types in test benches?

Answer 12

bit, logic, byte, int

Question 13

What is the string data type?

Answer 13

An ordered collection of characters that can be dynamically sized. The class comes with many of the typical C-style string functions: atoi, putc, compare, substr, len, etc.

Question 14

What is the enum data type?

Answer 14

A set of named values

Question 15

How to declare an enum?

Answer 15

enum {RED, YELLOW, GREEN} light;

Question 16

What is an enum example?

Answer 16

module tb;
  typedef enum {T,F} e_b;
  initial begin
    e_b P;
    P=T;
    $display("P=%s",P.name);
  end
endmodule

Question 17

What are the types of arrays in SystemVerilog

Answer 17

Packed and unpacked

Question 18

What is a packed array?

Answer 18

A packed array is used to refer to dimensions declared before the variable name.

A one dimensional packed array is also called a vector.

They can be made of only the single bit data types like bit, logic.

Question 19

How to declare a 2D packed array?

Answer 19

bit [3:0][7:0] m_data;

Question 20

What is an unpacked array?

Answer 20

An unpacked array is used to refer to dimensions declared after the variable name.

Unpacked arrays may be fixed-size arrays, dynamic arrays, associative arrays or queues.

Question 21

What is a dynamic array?

Answer 21

A dynamic array is an unpacked array whose size can be set or changed at run time

Question 22

What is an associative array?

Answer 22

Associative arrays do not have any storage allocated until it is used, and the index expression is not restricted to integral expressions, but can be of any type.