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Architecture and Operating Systems > CPU (PPT 7 - 10) > Flashcards

CPU (PPT 7 - 10) Flashcards

1
Q

What is in memory?

A

Memory consists of a series of numbers stored at numbered locations. Contiguous blocks usually contain:

  • A sequence of numbers, forming a machine code program
  • Collections of numbers which are user data
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2
Q

What is the Fetch Execute Cycle?

A

The CPU fetches in a number, interprets this number by decoding it and getting the operation and the operand.

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3
Q

What does an instruction consist of?

A 
A single instruction is made up of:
An opcode
and possibly:
An Operand
An Addressing Mode
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4
Q

What is the Instruction Set?

A

The instruction set defines the operations which a microprocessor can perform

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5
Q

What are some examples of operations an Instruction Set contains?

A 
Data transfer
Arithmetic
Logical
I/O
Flow Control
System Control
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6
Q

What are some of the additions to the Instruction Set over the years?

A

More arithmetic operations have been added, such as trigonometric functions and logarithmic functions. or the ability to use real numbers
Signal processing operations, such as for audio and video

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7
Q

What is SIMD?

A

Single Instruction Multiple Data is when we pack two samples into one register and process both samples together, saving time.

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8
Q

What is the Addressing Mode?

A

Specifies where to find the operand for an instruction. Can be immediate, stored in the registers or in main memory.

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9
Q

Why do we need multiple Addressing Modes?

A

We need a range of modes to be able to reference as large a range of locations in memory as flexibly as possible

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10
Q

What happens if the required operand is stored in main memory?

A

The processor must calculate the physical address of the data using one of the addressing modes.

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11
Q

What are the different types of addressing mode and what are the trade offs?

A 
Immediate
Direct
Indirect
Register
Register Indirect
Displacement
Stack
Each trade off between address range and/or flexibility and the number of memory references and/or complexity of the address calculation
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12
Q

What is the immediate addressing mode?

A

Data is packed into the code

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13
Q

What is the register addressing mode?

A

Data is in the register named in the code?

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14
Q

What is the direct addressing mode?

A

Data is at the address indicated by a pointer named in the code

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15
Q

What is the displacement addressing mode?

A

Data is at the address indicated by a pointer and displacement named in the code

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16
Q

What is the stack addressing mode?

A

Data is at the address indicated by the stack pointer

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17
Q

What is an advantage and disadvantage of direct addressing and give an example?

A

Example: simple variables
Adv: simple
Disadv: limited addressing to one instruction

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18
Q

What is an advantage and disadvantage of indirect addressing and give an example?

A

Example: arrays(pointer is the index)
Adv: Simple to access multiple addresses
Disadv: Access takes longer

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19
Q

What is an advantage and disadvantage of displacement addressing and give an example?

A

Example: records
Adv: Simple to access multiple addresses
Disadv: Access takes even longer

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20
Q

What is a stack?

A

Stack is used for storage of temporary variables. It is stored in part of the RAM. It functions like a separate data structure within the hardware.

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21
Q

How is the stack stored?

A

A contiguous block is reserved in main memory. Most of the time, the block is partially filled with elements and the remainder is available for stack growth.

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22
Q

What is the stack used for?

A

The stack is mainly used for the following things:

  • Temporary storage of variables
  • parameter passing to subroutines
  • Parsing syntax by compilers
  • Any application where flexibility of size and/or address less storage is needed.
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23
Q

Calculate the Physical Address if the Base Register contains $00156989 and the Start Register contains $00AA9673

A

PA = SR + B

00156989 + 00AA9673 = 00BFFFFC

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24
Q

Calculate the Physical Address if the Base Register contains $00133900 and the Start Register contains $00AA9673 and the Address field of the instruction contains 42

A

PA = SR + B + A

00133900 + 00AA9673 + 42 = 00BDCFBF5

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25
Q

Calculate the Physical Address if the Base Register contains $00145270 and the Start Register contains $00CD9271 and the Address field of the instruction contains 37. The Index Register contains 100 and the Scale Factor is 4

A

PA = SR + B + A + (I x S)

00145270 + 00CD9271 + 37 + ( 100 x 4 ) = 00E1EDC8

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26
Q

What does the Instruction Set of a Processor define?

A
  • Types of operations available
  • Types of operands available
  • Instruction formats available
  • Addressing modes available
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27
Q

What must an instruction contain for the CPU to execute?

A
  • Opcode
  • Operand references
  • Where to fetch the next instruction (This is usually implicit)
28
Q

What are the four types of Operand?

A
  • Addresses
  • Numbers
  • Characters
  • Logical Data
29
Q

What are the four General data types in a Pentium processor?

A
  • Byte
  • Word (16 bits)
  • DoubleWord (32 bits)
  • QuadWord (64 bits)
30
Q

What does CISC mean?

A

Complex Instruction Sets Computer
This means that single instructions can use increasingly complex addressing modes and functions. It also supported high level data structures but was slow to process some instructions

31
Q

What does RISC mean?

A

Reduced Instruction Set Computer
This means that the processor only supports simple addressing modes. The CPU will then be optimised to process these very fast but it means the compiler needs to do more work

32
Q

What are the benefits of expanding the following:
Opcode
Addressing Modes
Operands?

A

Opcode: Enlargement is useful as it allows the handling of additional instructions
Addressing Modes: Improves the flexibility of the processor to support compilers
Operands: Includes some operands within the instruction set, reducing the need to fetch operands

33
Q

What are the five types of processor?

A

Integer Processor

Maths Co-Processor

Combined Processors

Digital Signal Processors

Graphics Processors

34
Q

How does signal processing work?

A

Large amounts of data are fed through small code loops

35
Q

What is SIMD?

A

Single Instruction Multiple Data

This means that multiple data words are calculated on together, saving processor time

36
Q

What are the benefits of increasing word size?

A
  • Larger data can be handled in a single operation
  • More instructions are available, so we can do more with a single instruction
  • More addressing modes are available so increased flexibility and support for complex data structures
  • Small operands can be combined with opcodes, reducing the number of operand fetches which are required
37
Q

What is contained within the programmers model of a CPU?

A
  • What registers are available
  • What instructions are available
  • What addressing modes are available
38
Q

What are the steps of the fetch-execute cycle?

A

1) Instruction Fetch (IF)
2) Instruction Decode (ID)
3) Operand Calculation (OC)
4) Operation Fetch (OF)
5) Execute Instruction (EX)
6) Write Operand (WO)

39
Q

What is Pipelining?

A

We can design the CPU to have multiple instructions, at different stages of completion, inside the CPU at once

40
Q

What is Instruction Level Parallelism?

A

The time to process one instruction remains unchanged. However, the time between each instruction completion is shorter so the apparent time it takes to process an instruction is shorter.

41
Q

What stages of the Fetch-Execute cycle can be parallelized and why can’t the others be?

A

Instruction decode
Operand Calculation
Execute Instruction
The rest cannot be parallelized because they are memory bus operations

42
Q

How long does it take to complete a parallelized instruction?

A

It usually takes C/n clock cycles, with C being the fixed clock cycles and n being the stages.

43
Q

What can disrupt the flow of a pipeline?

A

The flow can be disrupted by dependencies, which can stall the execution of an instruction. At worst, it will cause the pipeline to be flushed and restarted.

44
Q

What are the two types of dependency?

A

Data dependency

Branch Dependency

45
Q

What is a data dependency?

A

This happens when the second instruction cannot complete until the first instruction has finished using a register

46
Q

What is a branch?

A

A branch is an instruction that can change the order of execution of instructions based on a condition. All branches are binary in machine code

47
Q

What is a branch dependency?

A

The CPU does not know which way a branch will go so it has to guess which way it will. If it guesses wrong, the incoming instructions are irrelevant and the CPU has to refill the path with the correct instructions, causing a stall.

48
Q

What are some solutions to branch dependencies?

A
  • Branch Prediction
  • Pre Fetch Branch Target
  • Multiple Streams
  • Loop Buffer
  • Delayed Branch
49
Q

What is Branch Prediction?

A

This tries to improve the CPU’s guesses when it encounters a conditional branch. It uses one of two ways:
static
dynamic

50
Q

What are the static methods of branch prediction?

A

Static methods predict that the branch will either always be taken or never be taken. This depends on the particular opcode of the branch instruction.

51
Q

What are dynamic methods of branch prediction?

A

Dynamic methods try to predict on the fly whether to branch or not. Predictions are based on the recent history of that particular branch instruction. This means that the CPU needs to keep track of the history of each conditional branch during execution of a program.

52
Q

What is a BTB?

A

Branch Target Buffer
This is a cache which stores the instruction’s address and the Branch Destination Address, which is the address the processor will branch to if it branches. The History Bits are two bits which record the recent history

53
Q

What happens to the BTB when a branch is encountered?

A

When a branch is taken for the first time, it is written to the BTB cache and the History bits are set to 11. When the instruction is re-encountered, the prediction is taken if History>0. Then, based on the actual outcome, the bits are incremented if it was taken and decremented if it wasn’t

54
Q

What are some limitations to the BTB?

A

If a branch would be taken every other time, the branch will always be predicted wrongly.

55
Q

How is the BTB used?

A

When a conditional branch instruction is fetched, the instruction decoder passes the address to the Branch Target Buffer, which makes a prediction whether it will be taken or not. The BTB supplies the predicted branch destination to the Instruction pre fetcher, from where the instruction fetch will be made

56
Q

Can predictions cause issues?

A

Yes, if a wrong prediction is made, the CPU must flush the pipeline and fetch the correct instruction, taking 3 to 4 cycles

57
Q

What is Super-Scalar Architecture?

A

This is the process of duplicating hardware components. We can duplicate:

  • pipelines within the CPU
  • whole CPU cores
  • the CPU itself
58
Q

What is thread-level parallelism?

A

This is using components in parallel with each working on their own instruction

59
Q

What are the five stages of the Pentium Integer Pipeline?

A
  • Pre Fetch Instruction
  • Decode Stage 1
  • Decode Stage 2
  • Execute
  • Write Back
60
Q

What happens at decode stage 1 and 2 of the Pentium Integer Pipeline

A

Decode 1: Identifies op code and extracts addressing information; also performs branch prediction, checks instruction pairing for pipelines

Decode 2: Calculates memory address (effective addresses)

61
Q

What is instruction pairing?

A

These are the rules which govern whether two instructions can be fed into two pipelines at the same time. These are:

  • There must be no dependency between the two instructions
  • V instruction must be simple

There are other more complicated restrictions to prevent stalling

62
Q

What is Simultaneous Multi Threading?

A

This is when CPUs run multiple threads internally, essentially creating two virtual cores within one real core

63
Q

What are the benefits of Simultaneous Multi Threading?

A

In theory, there would be increased efficiency as there will be no data dependencies between threads, so fewer stalls.

In practice, the reported speed and power consumption benefits can be variable

64
Q

Explain why there is not a linear increase in power when adding more cores or processors

A

It is not a linear increase due to the fact that not everything is parallelizable and there is an overhead due to the OS and processor managing multiple threads

65
Q

How can a CPU reduce power consumption?

A
  • Run at a reduced voltage (preferably dynamic)
  • Run at reduced clock speed (preferably dynamic)
  • Turn off parts of the CPU not being used
  • Compiler optimisations
66
Q

What is a Transputer?

A

It is a chip with a CPU, memory and communication hardware in one. It allows infinite scalability in theory, add another chip and double the power.

67
Q

What is FPGA?

A

Field Programmable Gate Array
This is like a writeable silicon chip. Any logic device can be built and tested (on a computer) and then burned into a FPGA. This allows cheap and quick production of custom made chips or even whole CPUs.

Architecture and Operating Systems (13 decks)

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