CPU performance, power, safety, and security Flashcards
What are the four stages in a CPU cycle? Which of these stages are performed by RAM?
Fetch, decode, execute, store (no storing stage in ARM7)
RAM does storing and fetching
What is a pipeline bubble?
A stage that isn’t performing useful work due to a lack of data from a early stage
What is latency and throughput? Which is increased by pipelining?
Latency: time for an instruction to get through the pipeline
Throughput: number of instructions executed in a time period
Throughput increased by pipelining
What is the cache for?
Immediate access to data
How does a bigger cache impact the computer?
Better performance
What is a cache miss?
When data is not found in the cache and computer must search the database
What is a compulsory miss?
The location has not been referenced before or the data has never been in the cache
What is a conflict miss?
Two locations are fighting for the same block, so some data was pushed out
What is a capacity miss?
The cache was too small for all the data, so some data was pushed out
How can latency from cache misses be reduced?
Use a sample policy to remove data less likely to be used.
What are the four sample policies for cache management?
- First in first out
- Last in first out
- Least recently used
- Most recently used
What factors do energy and power consumption impact?
Energy consumption impacts battery life.
Power consumption impacts heat generation.
Explain dynamic voltage and frequency scaling (DVFS) as a power management strategy
Reduce supply voltage when performance can be lowered. Use for dynamic power management.
Explain race-to-dark as a power management strategy
If power consumption is dominated by static power, run as fast as possible, then remove power supply from logic
What is the difference between static and dynamic power management?
Dynamic depends on CPU, static does not
