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CompTIA A+ Exam Prep > Computing Overview > Flashcards

Computing Overview Flashcards

1
Q

BIOS

A

Basic Input Output System. The fundamental firmware that initiates when the PC is powered on.

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2
Q

CMOS

A

Complementary Metal-Oxide Semiconductor. Where the BIOS is stored and backed up with a battery. Generally 128-512 bytes of content.

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3
Q

TPM

A

Trusted Platform Module. A security feature on the motherboard that manages cryptographic functions.

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4
Q

ATX

A

Advanced Technology Extended.

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5
Q

PCI

What’s the bus width and throughput?

A

Peripheral Component Interconnect.

Bus width:
32-bit and 64-bit

Throughput:

  • 133 MB/s (32-bit @ 33MHz)
  • 266 MB/s (32-bit @ 66MHz or 64-bit @ 33MHz)
  • 533 MB/s (64-bit @ 66MHz)
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6
Q

CNR

A

Communications and Networking Riser. Created to provide the option to add additional network cards or additional modems into the PC.

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7
Q

AGP

What’s the throughput?

A

Accelerated Graphics Port.

AGP 1x = 266MB/s
AGP 2x = 522MB/s
AGP 4x = 1.07GB/s
AGP 8x = 2.1GB/s

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8
Q

PCI-X

What’s the throughput?

A

PCI eXtended

1,064MB/s

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9
Q

What does the x16 in PCIe x16 mean?

A

The amount of full-duplex PCI Express lanes between the Northbridge and the memory slot.

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10
Q

What is the typical throughput for the various versions of PCIe?

A

v1. x = 250MB/s
v2. x = 500MB/s
v3. 0 = 1GB/s
v4. 0 = 2GB/s

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11
Q

SIMM

A

Single In-line Memory Module.

Electrical contacts are the same on both sides.

30 pin and 27 pin.

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12
Q

RIMM

A

Rambus Inline Memory Module.

16-bit = 184 pins
32-bit = 232 pins

Required every memory slot must be filled. For 16-bit modules the empty slots required Continuity RIMM (C-RIMM) and for 32-bit modules require a Continuity and Termination RIMM (CT-RIMM

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13
Q

DIMM

A

Dual In-line Memory Modules.

Electrical contacts are different on each side.

64 bit data width

SDRAM = 168 pins
DDR = 184 pins
DDR2/DDR3 = 240 pins
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14
Q

SO-DIMM

A

Small Outline Dual In-line Memory Module.

72-pin, 100-pin, 144-pin, 200-pin, 204-pin.

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15
Q

DIP

A

Dual In-line Package CPU type.

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16
Q

SECC

A

Single Edge Contact Certridge.

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17
Q

PGA

A

Pin Grid Array.

18
Q

ZIF Socket

A

Zero Insertion Force socket.

19
Q

LGA

A

Land Grid Array.

Pins are on motherboard.

20
Q

Northbridge

A

AKA Memory Control Hub. Connects the CPU to memory and high-speed graphics card.

21
Q

Southbridge

A

Manages connections such as PCI slots, USB, Ethernet, IDE, Onboard graphics controllers, BIOS, etc.

22
Q

Different types of ROMs

A

Read-only memory. Cannot be changed or erased.

PROM: Programmable ROM - Write once.

EPROM: Erasable PROM - Write/Erase/Write again

EEPROM: Electrically Erasable PROM - Flash memory.

23
Q

SRAM

A

Static RAM. Very fast, big and expensive memory.

Used often in processor cashes like L1, L2, L3.

No refreshing, but still volatile.

24
Q

DRAM

A

Dynamic RAM.

Needs constant refreshing, without it, the data in the memory disappears.

25
Q

SDRAM

A

Synchronous Dynamic RAM.

Synchronous with the common system clock.

Ex: 133MHz clock = PC133

26
Q

RDRAM

A

Rambus Dynamic RAM.

Relatively more expensive than SDRAM because of the Ramus and Intel partnership.

27
Q

DDR-SDRAM

A

Double Data Rate Synchronous Dynamic RAM.

To figure out the peak data rate, multiply the memory bus clock rate by 16.

Ex: 1,600MB/s = PC-1600

28
Q

DDR2

A

Enhanced electrical interface, buffers, off-chip drivers.

To figure out the peak data rate, multiply the memory bus clock rate by 32.

Ex: 3,200MB/s = PC2-3200

29
Q

DDR3

A

Twice the data rate of DDR2 with larger chip capacities.

To figure out the peak data rate, multiply the memory bus clock rate by 64.

Ex: 6,400MB/s = PC2-6400

30
Q

CAS

A

Column Address Strobe/Select.

The delay between the time that the memory controller requests some data from RAM and the moment the data is available on the memory module’s output pins. In SDRAM, the CL is specified in clock cycles.

31
Q

CL

A

CAS Latency.

Clock cycles between a memory request sent and data received.

The lower the CL number, the fewer clock cycles and faster the data transfer.

32
Q

ECC

A

Error Correcting Code memory.

Memory that detects and corrects errors.

33
Q

Parity Memory

A

Memory that checks itself for errors utilizing a parity bit, but cannot correct the error and won’t always detect the error.

34
Q

MBR

A

Master Boot Record.

The first sector of a hard drive (usually only 512 bytes).

Contrains:
Table of primary partitions, disk signatures, directions for starting the operating system.

35
Q

USB

A

Universal Serial Bus.

36
Q

FireWire

A

AKA IEEE 1394, i.LINK or Lynx.

Connects up to 63 devices.

FireWire 400 aka Alpha Mode or IEEE 1394a = 100, 200, 400 Mbit/s half-duplex.

FireWire 800 aka Beta Mode or IEEE 1394b = 800 Mbit/s full-duplex.

37
Q

SATA

A

Serial Advanced Technology Interface (internal)

38
Q

eSATA

A

External Serial Advanced Technology Interface

39
Q

PATA

A

Parallel Advanced Technology Attachment

Used to be IDE = Integrated Drive Electronics.

2nd Generation, EIDE
Enhanced IDE.

16MB/s - 133MB/s

Connected with 40-wire or 80-wire motherboard connectors.

40
Q

ATAPI

A

ATA Packet Interface.

A PATA connection for other drives such as CD drives.

41
Q

Master Drive

A

Device 0

Closest to the motherboard with the 40 cable connector, furthest from the motherboard with the 80 cable connector.

42
Q

Slave Drive

A

Device 1

Closest to the motherboard with the 80 cable connector, furthest from the motherboard with the 40 cable connector.

CompTIA A+ Exam Prep (1 decks)

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