Computers and the Internet Flashcards
(233 cards)
1
Q
When may polling be preferable?
A
Polling may be efficient if:
- The controller and the device are fast
- The I/O rate is high
- Some I/O data can be ignored
- The CPU has nothing better to do
2
Q
Explain Large Data Transfers in Devices
A
-Some devices (e.g., disk drives) will often do large data transfers
-The transfer will be inefficient if the CPU has to feed data, byte by
byte, to the controller’s registers
- A better approach is to offload this work to a special-purpose
processor (a direct memory access (DMA) controller)
3
Q
What are device drivers?
A
A device driver hides differences between various device controllers by defining an interface between the OS and I/O devices for a specific class of I/O devices.
3
Q
What is Direct Memory Access?
A
-The CPU writes command block into memory, specifying source and destination of transfer
-The DMA controller can then perform multiple transfers via a single command
-When the transfer is complete, the CPU receives an interrupt from the DMA controller
-This enables the CPU to spend more resources on other tasks
4
Q
What are System Calls?
A
A request of a kernel service.
5
Q
What is a Character I/O
A
(Examples: keyboards, computer mice, microphones, speakers)
- A character device transfers byte one by one
- Characters must be processed in order that they arrive in the
stream
6
Q
What does Character I/O interface include?
A
The interface includes
- Get operation, to return the next character in the stream
- Put operation, to add character to stream
- Libraries for line-by-line access, with integrated editing services (e.g.,
use back spaces to remove the preceding character from the
stream)
7
Q
What is Block I/O?
A
Block devices (typically non-volatile mass storage devices) are used to transfer blocks of data.
They are high volume devices
8
Q
What does Block I/O interface include?
A
The interface includes:
- Read operation, for reading blocks of data
- Write operation, for writing blocks of data
9
Q
How does does Block I/O access Memory-Mapped Files?
A
Layered on top of block device drivers
Rather read/write, it provides access to disk storage via a location in main memory
The OS deals with transferring data between memory and the device and can perform transfers when needed
10
Q
What does a network socket interface have system calls for?
A
- Creating and connecting sockets
- Sending and receiving packets over the connection
- Select function, for determining the status of one or more sockets
(whether the socket is ready for reading or writing )
11
Q
What is the main difference between network I/O device and other I/O devices?
A
With network I/O devices things routinely go wrong (missing packets, etc.)
Therefore, there need to be a system functions for:
- Checking whether a transfer was successful
- Recovering gracefully from unsuccessful transfers
12
Q
Define a program
A
A set of instructions for performing a specific task and is stored on a disk (passive)
13
Q
Define a process
A
An instance of a program, in execution (active) - requires CPU resources, memory and I/O
Multiple process instances of one program
14
Q
Why use processes?
A
Modularity:
- Simplifies OS development and maintenance
Speedup through Parallelism:
- Execute multiple processes in parallel using multiple CPU cores
Security and Stability through Isolation:
- Usually, each process operates in its own memory space
- Minimize inter-process disruptions – problems in a process may not
affect others
15
Q
What is a Process Control Block (PCB) ?
A
A PCB is a data structures that stores all the information about a process
- Kernel’s representation of a process
16
Q
How does Context Switching work?
A
Stop running process 1 and start process 2:
- Change the state of process 1 from running to ready
- Save the context of process 1
- Load the context of process 2
- Change the process scheduling state of process 2
17
Q
What is the tradeoff of Context Switches?
A
With too few context switches
- No fairness between processes – some processes may have to wait for a long time
With too many context switches
- The processor will spend too much resources on overhead
18
Q
Key info about the stack structure
A
LIFO structure
Operations: Push and Pop
Function Call: Activation record (parameters, local variables, return address) pushed to stack
Function Return: Activation record popped from stack
19
Q
Key info about the heap structure
A
- Dynamically allocated like the stack
- Blocks of memory are allocated and removed in an arbitrary order
Used when you need:
- To store a large block of memory for a longer period of time
- Variables that can change size dynamically
20
Q
What is Process Hierarchy?
A
In Unix-like systems there is a hierarchy of processes
21
Q
What is process spawning?
A
The method by which a process (parent) creates a new process (child)
- In linux there are 4 system calls for process spawning:
- fork()
- wait()
- exec()
- exit()
22
Q
Define a Preliminary
A
- A process is a program in execution
-Processes change their state over the process lifecycle
23
Q
What is a process scheduler?
A
Process schedular allocates CPU time to various processes
24
What are 4 scheduling algorithms?
First Come First Served (FCFS)
Round Robin (RR)
Shortest Process Next (SPN)
Multilevel Queing
25
What is the key info of a FCFS?
FIFO - Processes get executed in order arrived
Non-preemptive - Not interrupted until finshes or reaches a wait state
26
What are the Pros and Cons of FCFS?
Pros:
1. Simple and easy to implement
2. Reduced Context Switching
3. Intuitively fair
4.No starvation
Cons
1. Convoy Effect - Long waiting time and poor responsiveness
27
What is the key info of a Round Robin?
Time-sliced (quantum) FIFO execution
Preemptive
28
What are the pros and cons of the Round Robin
Pros:
Fair CPU Allocation
Responsiveness
No Starvation
Cons:
Time Quantum Sensitivity
Context Switch Overhead
29
What is the key info of a SPN?
Select the process with the shortest execution time
Non-Preemptive – Preemptive (Shortest Remaining Time)
30
What are the pros and cons of the SPN?
Pros:
Better average waiting time
Responsiveness
Cons:
Estimating process execution time
May lead to starvation
Longer processes wait longer
31
What are the pros and cons of Multi-level Queuing?
Pros:
Supports different performance objectives
Cons:
Complex and difficult to calibrate
32
What is Multi-level Queueing?
- Processes are divided into different queues based on their priority and characteristics.
- Each queue has its own scheduling algorithm.
- Improves efficiency by grouping similar processes and handling them with specialized algorithms.
( Commonly used to manage and prioritize different types of processes, such as interactive and batch processes )
33
What is a multi-core processor?
- A multi-core processor has multiple processing units (cores) on a
single CPU chip
- Each processor/core has its own L1 cache memory
- There is a cache hierarchy
34
What are the two types of efficient Multi-Processor Scheduling?
Load Balancing
Processor Affinity
35
What is Load Balancing?
Evenly distribute processes among CPU cores
36
What is Processor Affinity and Soft Affinity
Processor Affinity: Keep a process on the same CPU core(s)
Soft Affinity: Only move processes if there is a good reason
37
What is Monoprogramming?
Single Process
38
What is Multiprogramming?
Multiple Processes
39
What are the 3 memory Management Tasks?
1. Relocation
2. Protection
3. Sharing
40
Define Relocation
Moving a process to a new location in memory without disrupting its execution
41
Define Protection
User processes need to protected from each other
System processes should be protected from user's processes
42
Define Sharing
Processes may sometimes need to share data
43
What are the 6 Memory Management Techniques
1. Fixed Partitioning
2. Dynamic Partitioning
3. Simple Segmentation
4. Virtual Memory Segmentation
5. Simple Paging
6. Virtual Memory Paging
44
What is the key info on Fixed/Static Partitioning?
Memory divided into partitions of fixed boundaries (equal or unequal sizes)
1-to-1 mapping of partitions and processes
Process loaded into partitions ≥ its size
45
What are the pros and cons of Fixed Partitioning?
Pros:
Easy to uunderstand and implement
No external fragmentation
Cons:
Internal Fragmentation
Limited by number & size of partitions
46
What is the key info of Dynamic Partitioning?
Exact memory allocation – only what is needed
- Partitions of variable length and number
- 1-to-1 mapping
Starts well, then leads to external fragmentation
47
Define External Fragmentation
Space is wasted between partitions
48
Define Compaction
Shift processes for unified free memory space
49
What are the pros and cons of Dynamic Partitioning?
Pros:
No internal fragmentation
Efficient than static partitioning
Cons:
External fragmentation
Overhead of compaction
50
What is the key info of Single Segmentation?
Processes divided into segments
Segments are loaded into memory as in partitioning
Segments do not need to be contiguous
51
What is the key info of Virtual Memory Segmentation?
Virtual memory use disk space to extend main memory; illusion of larger memory
Segments can be swapped between memory and disk storage
OS loads segments into memory as needed
52
What are the pros and cons of Virtual Memory Segmentation?
Pros
Can fit processes larger than memory
Segment Sharing and Protection
No internal fragmentation
Efficient than static partitioning
Cons:
More complex memory management
External fragmentation (< dynamic)
Overhead of compaction
53
What is the key info of Simple Paging?
Memory divided into equal size frames
A process is divided into same-size pages
Internal fragmentation is small since:
- only affects the last frame of each process
- the frame/page-size is fairly small
54
What are the pros and cons of Simple Paging?
Pros:
No External Fragmentation
Simple memory allocation
Cons:
Small Internal Fragmentation
Page tables can become large
55
What is Virtual Memory Paging
Pages are loaded into frames as in simple paging, except, that not all the pages need to be loaded at the same time
56
What are the pros and cons of Virtual Memory Paging?
Pros:
Can fit processes larger than memory
No external fragmentation
Simple memory allocation
Cons:
Virtual Memory overhead
Small Internal fragmentation
Page tables can become large
57
What are the goals of Protection & Sharing (with Segmentation and Paging) ?
Protection: Each process can only access its own pages/segments
Sharing: Multiple processes can access the same page/segment
58
How is Protection & Sharing implemented (with Segmentation and Paging) ?
Each frame/segment has a number of protection bits specifying
Read, write, execute permissions, which processes have these permissions
59
What is the result of Protection & Sharing when using segmentation instead of paging?
Protection/sharing is generally easier with segmentation than paging since:
- Segment table is smaller than page table
- Segments are more natural units for protection/sharing
60
How do Positional Numeral Systems work?
The contribution of a digit to the value of a number is the value of the digit multiplied by a factor determined by the position of the digit
61
What is the key info for the octal system?
Base 8
Easier shorthand for binary
An octal represents 3 bits.
62
What is the Memory Hierarchy?
Speed (Top to bottom):
Registers
Cache
Main Memory
Disk
Size (Top to bottom):
Disks
Main Memory
Cache
Registers
63
What are the main components of a computer?
1. Disk Controller
2. USB Controller
3. Graphics Controller
4. CPU
5. Memory
64
What is the key info of the CPU?
Controls the execution of instructions
A CPU will use a specific instruction set architecture (ISA), such as ARM or x86
65
Define a register
Small, fast memory locations within the CPU
66
What are the different types of registers?
- General purpose registers: data storage, address calculations and
arithmetic operations
- Special purpose registers: Program counter, Base pointer, Stack
pointer, Link register, Current program status register
67
How does the Stack pointer work?
Points to the top of the stack
68
How does the Base pointer work?
Points to the start (base) of the current frame
69
How does the Link Register work?
Stores the return address for after function completion
70
How does the program counter work?
Stores the address of the next instruction to be executed
71
How does the ALU work?
Handles arithmetic and logical operations
72
What does the current program status register do?
Contains status and mode bits
73
What is assembly language?
Simple instructions
Difficult programming language
74
What is branching?
Branch instructions will "jump" to a different instruction
They do so by changing the program counter
75
What is Temporal Locality?
Items accessed recently are likely to be accessed again soon
- Example: loops
If you want to discard data, start with one that has not been request in a long time
76
What is Spacial Locality?
Items located near each other in memory are likely to be accessed within a short period of time
- Most programs exhibit spatial locality
Copy additional nearby memory locations into the cache
77
What are Hits and Misses?
A memory request may be a:
- Cache hit – the cache contains the data (faster data return)
- Cache miss – the cache does not contain the requested data – first
read from memory
78
What are the 3 Cache Designs?
1. Direct Mapping
2. Fully-associative Mapping
3. Set-associative Mapping
79
What is the key info of a Directed-Mapped Cache?
Each block of main memory maps to one unique cache line
Each line connects the connects the corresponding block of cache memory to each block of main memory
80
What are the pros and cons of a Directed-Mapped Cache?
Pros:
Simple, Easy to implement & search
Cons:
Inefficient use of the cache space
81
What is the key info of a Fully-Associative Cache?
Each block of main memory can map to any line of the cache
Replacement algorithm: LRU (Least Recently Used)
82
What are the pros and cons of a Fully-Associative Cache?
Pros:
Flexible
Cons:
Takes a long time to search
83
What is the S-Way Set-Associative Cache
The cache is divided into N cache sets
Each cache set consists of S lines
Each block of main memory maps to one unique cache set
Replacement algorithm: LRU (Least Recently Used)
84
What are write hits and write misses?
A write request may be a:
- Write hit – the address we want to write to is present in the cache
- Write miss – the address we want to write to is not present in the
cache
85
How would you deal with a Write Hit?
For a write hit, there are two options:
- Write-back – initially write only to cache
- Write into memory if being replaced
- Pros: fast writes
- Cons: mechanism for cache coherence
- Write-through – write into both cache and memory
- Pros: consistency between the cache and memory
- Cons: slow writes
86
How would you deal with a Write Miss?
For a write miss, there are two options:
- Write around (no-write allocate) - write into memory only
- Pros: Avoids unnecessary cache access and cache pollution
- Cons: Does not utilize temporal locality
- Write allocate – fetch from memory and write into cache
- Pros: exploits spatial and temporal locality
- Cons: Potential unnecessary cache access and cache pollution
86
Whats the result of a High Temporal Locality and a Low Temporal Locality?
High Temporal Locality: Write-Back + Write Allocate
Low Temporal Locality: Write-Through + Write Around
87
What is Virtual Memory?
Use disk storage as if it was main memory
88
Define Demand Paging
Only load a page when there is a request for it
89
What are the pros and cons of Demand Paging?
Pros:
More processes can be loaded into main memory
Cons:
Thrashing - the CPU spends too much time on swapping pages
90
Define Pre-Paging
Guess which pages will be requested and pre-load them
91
What are the pros and cons of Pre Paging?
Pros:
Less overhead when page predictions are accurate
Cons:
Resources are wasted on loading unused pages
92
What is a Non-pipelined Cycle?
The time required to execute an instruction is the sum of the time required by each stage
93
What is a Pipelined Cycle
Where multiple stages of a task are completed simultaneously, each stage handled by a different part of the system
(allowing for continuous and efficient workflow).
94
What are the Pipeline performance measures?
Clock Cycle Time - time within which each pipeline stage must complete its operation
Clock Speed - frequency CPU's clock runs (1/Clock Cycle Time)
Execution Time - Clock cycles for program x Clock cycle time
95
What are the two main hazards of pipelining?
Control Hazards
Data Hazards
96
What is a Control Hazard?
A control hazard occurs when a branch instruction changes the next instruction
97
How would you deal with Control Hazards?
Ways to deal with control hazards:
1. Stall the pipeline
2. Assume the branch not taken
3. Branch prediction
98
What is Stalling the Pipeline?
Stop fetching and executing next instructions until branch result becomes known
99
What are the pros and cons of Stalling the Pipeline
Pros:
No need to do anything
Cons:
Wasting time and resources
100
What is "Assume Branch Not Taken" ?
Processor assumes branch not taken
Squashing instructions if wrong
101
What are the pros and cons of Assuming Branch Not Taken?
Pros:
No need to guess the next instruction
Cons:
Wasting time and resources if branch taken
102
What is Branch Prediction?
Processor may try branch prediction based on past branches
If the prediction is incorrect, instructions are squashed.
103
What are the pros and cons of Branch Prediction?
Pros:
Can reduce wasted clock cycles
Cons:
Branch prediction overhead
104
Define Data Hazard
When an instruction requires a result from a previous instruction before that result has been computed/written.
105
What are the 3 Data Hazard Types?
Read After Write (RAW) - True Dependency
- Instruction writes, then another reads same location
- Hazard if read happens before write completes
Write After Read (WAR) - Anti Dependency
- Instruction reads, followed by another writing to same location
- Hazard if write completes before the read
Write After Write (WAW) - Output Dependency
- Two instructions write to the same location
- Hazard iuf write occur in reverse intended order
106
What is the side effect of Deeper Pipelines
More pipeline stages means:
- a larger penalty for incorrect branch predictions
- a bigger risk of data hazards
107
What are the two ways for a processor to get more done per clock cycle?
1.Caching
2. Pipelining
108
Define Caching
A processor fetches instructions and data from cache and memory if possible
109
Define Pipelining
The execution of an instruction is divided into multiple stages
110
Define Control Hazards
Control hazards occur due to branch instructions
111
What are the similarities and differences of Spectre and Meltdown
Similarities:
- Exploit built-in vulnerabilities, not bugs
- Require attacker to be using the system
Differences:
- Spectre reads memory from other processes
- Meltdown can also read kernel memory from user space
112
What is Parallel Computing?
Improve performance by performing multiple computations in parallel
113
What are 5 examples of Parallel Computing?
1. ILP - Pipelining
2. Threads
3. Multi-core processors
4. Multiprocessors
5. Multicomputers
114
What is Processor Frequency Scaling?
Due to physical and thermal limitations, clock speeds cannot be increased indefinitely
115
What is Flynn's Taxonomy?
A classification of computer architectures based on number of instruction and data streams they can handle simultaneously
116
Define an Instruction Stream
Sequence of instructions; arithmetic, data transfer, and branching
117
Define a Data Stream
Consists of operands (constants, variables, and memory addresses)
118
Define Single Instruction, Single Data (SISD)
Sequential computer with no data or instruction parallelism
(Example: Older single-core CPUs & simple microcontrollers)
119
Define Multiple Instruction, Single Data (MISD)
Multiple instructions operate on one piece of data simultaneously
- Used for fault tolerance
- Rare in practice
(Example: Space shuttle flight control systems)
120
Define Single Instruction, Multiple Data (SIMD)
Execute the same instruction on multiple data points simultaneously
121
What is a Graphics Processing Unit (GPU)?
A GPU contains many ALUs to perform mathematical operations in parallel
(Based on SIMD architecture)
122
Compare GPU's to CPU's
GPUs have more ALUs and rely less on cache
GPUs have a high throughput and higher latency
123
What is the key info on Threads?
GPUs hide latency by utilizing threads
A process may be divided into multiple threads
Threads within a process share data, heap, and code, but have their own registers and stack
124
Define Multiple Instruction, Multiple Data (MIMD)
Multiple processors simultaneously execute different instructions on different pieces of data
125
Define a Multi-core Processor
A multi-core processor puts many CPU cores on one chip
126
Define a Multiprocessor
Two or more CPUs within a single computer system
CPUs communicate through shared memory variables
127
Define a Multi-Computer
Different computers connected together
128
Shared vs Distributed Memory
Shared (multiprocessors)
- Processors communicte through the shared memory
- Faster communication
Distributed (multicomputers)
- Processors communicate by passing messages
- Allows for higher bandwidth
129
What are the two energy problems the world faces?
1. Greenhouse gas emissions
- Energy generates 87% of global greenhouse gas emissions
- Richest countries have most emissions
2. Energy Poverty
- Low emissions of the poor as they lack access
- No electricity prevents key needs such as refrigiration and lights at night
130
What is the solution to emissions of greenhouse gas?
Reducing greenhouse gas emissions
- Shifting to renewable energy sources
- Phasing out fossil fuels and other high emission transport and industrial
practices
- Improving energy efficiency
Removing gases from the atmosphere
- Ecosystems like forests and wetlands that absorb CO2-
- Using technologies like carbon capture and storage (CCS)
131
What is the Energy Demand for ICT (Information and Communication Technology) by 2030 ?
ICT energy demand might rise to 8% of total electricity demand by 2030 at best case, or worst case rise to 21%.
In 2020, ICT secotr used an estimated 4-6%.
132
What is "The Quick and the Dead" ?
Historically, the processor world consisted of the quick (those with high SPECs) and the dead (those without).
133
What is "The Energy-Efficient and the Dead" ?
Today, the processor world increasingly consists of the energy-efficient (those with high SPEC marks/watt) and the dead (those without).
134
What is the Sleep State?
Up to 1990, there were 2 states: On, Off
Intermediary states; e.g. a sleep state with:
- low power consumption
- quick recovery to active state based on user output
135
What is Advanced Configuration & Power Interface (ACPI) ?
A standard device configuration and power management by the OS
It allows the OS to control the amount of power supplied to various devices using different power states
136
What are the 4 ACPI states?
1. Global
2. Device
3. Processor
4. Performance
137
What are the Global States G0-G3?
Apply to the entire system and are visible to the user
G0: Powered on (Working)
G1: Sleeping
- S1: Power On Suspend (POS)
- S2:CPU Powered off
- S3: Stand by
- S4: Hibernation
G2: Powered off (Soft Off)
G3: Unplugged (Mechanical Off)
138
What are the Device States D0-D3?
States of particular devices (e.g. disks, keyboards); generally, not visible to the user
D0: Fully Operational
D1: Intermediate states
D2: Device is off
139
What are the Processor States C0-C3 ?
Processor power consumption and thermal management states – Substates of G0
C0: Fully operational
C1: Ready — short wake time
C2: Ready — long wake time
C3:Sleep
140
How do Performance States P0-P15 work?
Power consumption and capability states within the active states (substates of D0/C0)
A processor could save energy by scaling down power and
clock frequency (P0 ⇒ P1, . . . , P15)
141
What is Power Usage Effectiveness (PUE) ?
A metric used to determine the energt efficiency of a data centre.
PUE = Total facility energy / IT energy
or
PUE = 1 + Non IT facility energy/IT equipment energy
142
What is the PUE scale/metric chart?
1.0 = Ideal
1.2 = Very efficient
2 = Average
2.5 = Inefficient
3 = Very Inefficient
143
What is the Open Compute Project (OCP)?
The OCP is a collaborative community focused on redesigning hardware to efficiently support growing demands on compute infrastrucutre
144
Define a Computer Network
Group of devices that are connected offer certain services
145
What are Hosts (end devices) ?
Source or destination of a message
Client or sever or both
Have unique physical and logical address
146
What are Intermediary Network Devices?
Connect hosts to the network, and connect networks together
147
Define peripherals
Don’t have logical address
Rely on their connected host to perform all network operations
148
What are the 3 types of Network Media?
Metallic "Copper" Wires (Electric pulses)
Fiber-optic Cable (Light pulses)
Wireless (Electromagnetic waves)
149
Define a LAN
Usually spans a single geographic area
Administered by a single organization
Characterized by high data speeds
May be a single local network or interconnected local networks
150
Define a WAN
Group of LANs interconnected within large area
TSP interconnects these geographical spanned networks
Characterized by slow data speeds
151
Define the Internet
Global mesh of interconnected networks
152
Define Communication Protocols
Just like humans, computers use protocols to communicate
153
Define Protocol Stack (Suite)
A group of interrelated protocols that are necessary to perform a communication function
154
Define Protocol Data Unit (PDU)
A generic term for data at each layer
155
Define Segmentation
The process of breaking data into pieces
156
Define Encapsulation
The process of adding control information to the data at each layer
157
What is the key info of Client Server model?
Client requests a service
Server offers a service
Centralized administration
158
What is the key info of Peer-to-Peer model?
A device acts as both the client and a server within the same communication session
No need for centralized server
159
What is Hypertext Transfer Protocol?
WWW is a massive collection of interlinked documents and resources
HTTP facilitates the transfer of these resources (e.g HTML files)
160
What are the 3 main HTTP methods and their descriptions?
GET - Retrieves data
POST - Submits data
DELETE - Deletes data
161
How is a web page loaded?
The client send HTTP requests to get other resources in the HTML file unless they are cached
162
What is HTTPS
Ensures the identity of the server and encrypts transmitted data
163
What is the Dynamic Host Configuration Protocol?
DHCP automates the assignment of IP address, Subnet mask, Default gateway, DNS server
It selects the IP address from a pool of addresses and once used it returns to the pool to prevent running out of addresses
164
What are Telnet and SSH?
Both are Remote access protocols:
- Telnet transfers data as plain text
- Secure Shell offers a secure alternative
165
What is the key info for DNS?
Devices are labeled with numeric IP address
Domain names are names for the numeric IP addresses
DNS translates human-readable domain names into machine-readable IP addresses
166
What does URL stand for?
Uniform Resource Locator
167
What is Shared hosting?
An IP address mapped to multiple host names
168
What is Load balancing and redundancy?
A host name mapped to multiple IP addresses
169
What are the 4 DNS Requirements?
1. Scalability
2. Efficiency
3. Reliability
4. Maintainability
170
What is a Root DNS server?
Top level, represented by (.)
Thirteen logical root DNS servers
Redundancy: each logical root server refers to multiple physical ones
First point of contact if a DNS resolver can't resolve a name
171
What is a Top Level Domain Server?
Organizational (com, org, edu, gov, net)
Geographical (uk, us, fr, eg, sp, de)
Managed by ICANN (Internet Corporation for Assigned Names and Numbers)
172
What is an Authorative Server?
Holds the complete data for a domain's DNS records
Source of DNS responses
To ensure maintainability, Authoritative servers must be updated automatically
173
What are Domains and Sub-domains?
Web addresses may utilize multiple subdomains separated by periods (.) in a hierarchical fashion.
computerscience.exeter.ac.uk
computerscience = 4th level domain
.exeter = 3rd level domain
.ac = 2nd level domain
uk = Top-level domain
174
What does DNSSEC do?
DNNSEC adds a layer of trust on top of DNS
175
What is Assymetric Encryption?
Asymmetric encryption use a pair of keys (private and public)
Using the encryption key as the public key (private communication)
Using the decryption key as the public key (Signature verification of documents)
176
What is a Hash Function?
A hash function takes data of arbitrary size, M, an returns a fixed-size number, H(M)
177
What identifies what transport layer protocol should be used?
Application developer choose the transport layer protocol based on the requirements of the application
178
What is they info of TCP and UDP?
TCP:
Connection-oriented protocol
Reliable delivery with higher overhead and latency
(HTTP, FTP, Telnet SMTP)
UDP:
Connectionless protocol
Unreliable, minimal overhead and latency
(DHCP, RIP, TFTP, Online games, Video Streaming and VOIP)
179
What is the key info of Transport Layer Functions?
TCP and UDP Shared Functions:
Segmentation and Reassembly
Conversation Multiplexing using port numbers
Error detection
Additional TCP Functions:
Connection Establishment (3-way handshake)
Connection Management: Reliability (ack), Flow control and Error correction
Connection Termination (4-way handshake)
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What is Sender Segmentation and Encapsulation?
The transport layer divides data into pieces and adds a header for delivery over the network
UDP:
Header prodives for:
source and destination (ports)
TCP:
Header provides for:
Sources and destination (ports)
Sequencing for same-order delivery
Acknowledgement of received segments
Flow control and congestion management
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What are the Network Ports ?
Well-known ports (0 to 1023) – reserved for well-known services
Registered Ports (1024 to 49151): assigned for user processes & others
Dynamic or Private Ports (49152 to 65535): Dynamically chosen by a client when initiating a connection to a server
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What does the Transport Layer allow and what does the Network Layer allow?
Transport Layer allows end-to-end transfer of application data
Network (Internet) Layer allows end-to-end device communication
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What are 4 key ideas behind Host to Host communication?
1. Addressing
2. Encapsulation
3. Routing
4. Decapsulation
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What is an IPv4 Address?
Uniquely identifies a device on an IP network
32-bit broken into four octets using dotted-decimal format
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What is IPv4 Hierarchical Structure?
Prefix Length - number of bits reepresenting network portion
Subnet Mask - 1s represent network portion and 0s for host portion
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What are the types of IPv4 Addresses?
Network Address - all host portion bits are zeros (0)
Broadcast Address - al lhost portion bits are ones (255)
Host Address - Between network & broadcast (1-254)
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What is Subnetting?
Dividing a single address block into multiple logical networks
- Borrowing bits from host portion to network portion
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What is Borrowing Bits in a Subnet?
The process of taking bits from the host portion of an IP address and using them to create additional subnets within a given network.
This technique allows network administrators to divide a larger network into smaller, more manageable sub-networks.
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Define a Public address
Addresses used in networks accessible on the Internet
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Define a Private address
Addresses used in internal networks aren't routable on the Internet
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What does NAT do?
Changes a private IPv4 address to a public address so it has internet access
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What is Internet Control Message Protocol (ICMP)?
Messaging protocol - sends messages and operational information
Used for error reporting and diagnosing network issues
- Testing connectivity (ping)
- Observing the path (tracert)
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What are 4 Device Configurations?
1. IP address
2. Subnet Mask
3. Default gateway
4. DNS Server
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What is the Internet of Things (IoT) ?
Network of physical objects - for connecting and exchanging data over the internet
The IoT is increasing the demand for IP addresses
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What is IPv4 Exhaustion?
Most IPv4 addresses have been used and therefore they are running out
As there are only 2^32 combinations.
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What are 3 ways to conserve IP addresses?
Classless Inter-domain Routing (CIDR) – Classless addressing
Public and private IPs
Network Address Translation
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What does CIDR do?
Reduces the waste of IP addresses
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What are 4 features of IPv6?
1. Large Address Space
2. Simplified Header
3. Built-in security
4. Jumbo grams
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What is the format of IPv6?
8 blocks of 4 hex digits
2001:0db8:0000:0042:0000:0000:abcd:ef12
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What is abbreviation of IPv6?
Discard Leading zeros in blocks
Double colon for consecutive zeros - Done once
2001:db8:0:42::abcd:ef12
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What does EUI-64 do?
Automatically generates a unique 64-bit interface ID
However is not recommended due to privacy issues
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What is the use of Jumbo grams?
Using jumbo grams in situations with low risk of transmission failure can reduce communication overhead
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What is a simple rule for Network Communication?
Works badly if two or more computers send messages at the same time
Works well if one computer sends a message at a time (for a limited period of time)
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What are the 2 types of Multiple Access Protocols?
Carrier sense, multiple access/ collision detection (CSMA/CD), for wired networks
Carrier sense, multiple access/ collision avoidance (CSMA/CA), for wireless networks
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CSMA/CD: Carrier Sense and Multiple Access
In a CSMA/CD wired network:
- All computers are attached to a shared cable – Multiple Access (MA)
- Any computer may transmit if the cable is unused – Carrier Sense
(CS)
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CSMA/CD: Collision Detection and Waiting Time
In a CSMA/CD wired network:
- While transmitting, a computer may detect that its receiving a
message – Collision Detection (CD)
- After detecting a collision, a computer waits for a random interval
(chosen from an exponentially-doubling range), and then tries again
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Why is CSMA/CD rarely used today?
As modern Ethernet variants avoid collisions by operating in full-duplex mode
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CSMA/CA: Carrier Sense and Multiple Access
In a CSMA/CA wireless network:
- All computers use a shared frequency – Multiple Access (MA)
- Any computer many transmit if the frequency is clear – Carrier
Sense (CS)
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CSMA/CA: Collision Avoidance
In a CSMA/CA wireless network:
- Frequency clear = transmits after an instant
- Frequency busy = counts down from random value while channel is
clear; otherwise, the count is frozen – Collision Avoidance (CA)
- Computer then transmits and receives an acknowledgement
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What is the Hidden Node Problem?
A computer may be in range of the base station, but out of range of another computer
This may be solved by reservation using ready to send and clear to send messages
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What is the Token Ring Protocol?
A token continuously circulates, to which messages may be attached, and from which they may be removed
Token Bus - The token is passed around a virtual ring
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What is the Bit-Map Protocol ?
Host n may announce that is has a frame to send by inserting a 1 bit into slot n
Following this, hosts begin to transmit frames in numerical order
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What is the Binary Countdown protocol?
Hosts that wish to transmit broadcast their binary address. Hosts with "1"s in their address get priority. The winner of the bid gets to transmit a frame.
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What is a network gateway?
Modern networks have a single fortified point of entry/exit
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List 4 Firewall Characteristics
A firewall can:
- Restrict both incoming and outgoing traffic
- Use both positive and negative filters
- Consider both the payload and different TCP/IP headers
- Consider packets individually or as part of a flow
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What are the 4 types of Firewalls?
The principal types of firewalls are:
1. Package-filtering Firewalls
2. Stateful packet inspection Firewalls
3. Application-level Gateways
4. Circuit-level Gateways
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Define a Packet-Filtering Firewall
Filters individual packets on the basis of the packet headers and packet payloads
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Define a Wildcard Mask
A wildcard mask indicates which bits of an IP address a particular rule is concerned with during IP address matching.
- 0: The corresponding bit must match
- 1: The corresponding bit doesn't matter
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Define a Stateful Firewall
Same as a packet filtering firewall, but also filters packets on the basis of a directory of established transport-layer connections.
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What is a Application-Level Gateway?
An application-level gateway filters packets based on applications or certain features of applications
Sets up two TCP connections: one from the trusted network to the firewall, and one from the firewall to the untrusted network
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What is a Circuit-Level Gateway?
A circuit-level gateway determines which TCP connections will be allowed. Just as the application-level gateway, a circuit-level gateway sets up two TCP connections.
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Define a Single Firewall Inline
Puts a firewall between external and internal router
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Define a Double Firewall Inline
Puts demilitarized zone (DMZ) between external and internal firewall. The DMZ is a network for systems that must be externally accessible, but still needs some protection.
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What is a Virtual Private Network (VPN) ?
Uses encryption and authentication to provide a secure connection through an otherwise insecure network – typically the internet
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What are the pros and cons of a VPN?
Pros:
Can be sued to bypass firewalls and other restrictions, and to increase privacy and security
Cons:
May result in lower connection speed, blocks from certain internet services, and realse of your data to third parties.
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What are the 4 rules that a IPv6 Address must follow?
1. Double colons cannot appear more than once, as it causes
confusion to how many zeros each double colon represents
2. Based on Hexadecimal therefore can only contain hex values
3. Maximum of 4 values between every pair of sequential colons
4. Must have 32 symbols (8 blocks of 4)
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A program requests 5 memory blocks which are all, one by one, brought into a 2-way set-associative cache. What is the case where
a) 2
b) 3
c) 4
d) 6
of the 5 memory blocks are still in the cache after the fth block has been placed?
a) All 5 have been mapped to same cache set
b) 4 have been mapped to same cache set
c) 3 have been mapped to same cache set
d) No more than 2 have been mapped to same cache set
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When initialising the IP header for a packet. Describe the disadvantage/risk of
i) a too small initial time-to-live value?
ii) a too large initial time-to-live value?
i) initial time-to-live value sets an upper limit on number of routers that the packet can pass before being discarded.
With a too small initial time-to-live value, the packet may be dropped before reaching its destination
ii) With a too large initial time-to-live value, there is a risk that the packet gets stuck in a routing loop, which will unecessarily consume bandwidth and may slow down the network.
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A HTTP request line (part of HTTP request) is not identical to a HTTP status line (part of HTTP response). Explain why.
i) only the request line specifies a method?
ii) only the status line specifies a status message
iii) both the request line and the status line specifiy a HTTP version?
i) The status line doesn't need a mathod, since the HTTP response is based on the method in the request line.
ii) The status message specifies the results of request. These results aren't available when HTTP request is sent, therefore not be a part of request line.
iii) The request line specifies the clients HTTP version the status line specifies the HTTP version used in the HTTP response.
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CSMA/CD uses a random waiting time with a range that doubles after each consecutive failed attempt. What would be the risk of
i) using a too long random waiting time?
ii) using a too short random waiting time?
iii) using a deterministic waiting time?
iv) not doubling the range after each failed attempt?
i) Amount of transmitted data will decrease, since stations will be waiting even though line is clear
ii) Network will be heavily loaded, and there will be an increased number of collisions
iii) 2 computers that have collided will get stuck in a loop where they wait for same length of time and collide again
iv) Typical waiting time won't adjust to the load of the network, and there is a risk that the network performance will drop significanlty if too many computers join network
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