Computer Systems Flashcards
Architecture that uses the same address for instructions and data
Von Neumann
Architecture that executes an instruction every 2 clock cycles
Von Neumann
Architecture that uses separate memory addresses for instructions and data
Harvard
Architecture that executes an instruction every clock cycle
Harvard
Architecture used in embedded systems
Harvard
Architecture used in computers
Von Neumann
Architecture with one bus
Von Neumann
Architecture with 2 buses
Harvard
Architecture that’s expensive but allows parallel access
Harvard
Architecture that is cheap but creates a bottleneck for buses
Von Neumann
Architecture used in cache memory
Harvard
Architecture used in main memory
Von Neumann
CISC
Complex Instruction Set Computer
RISC
Reduced Instruction Set Computer
Von Neumann
Everything kept together
Harvard
Everything kept separately
Instruction set uses as few lines of code as possible
Complex Instruction Set Computer CISC
Instruction set breaks down tasks into more simple instructions
Reduced Instruction Set Computer
Instruction set used in embedded systems
Reduced Instruction Set Computer RISC
Instruction set that combines load/store instruction within the instruction that carries out the actual calculation
Complex Instruction Set Computer CISC
Instruction set with one job to do
Reduced Instruction Set Computer RISC
GPU
Graphics Processing Unit. Has thousands of cores to process parallel tasks effectively. Works sequentially. Used for small, computer intensive tasks and can act together with CPU render graphics but also to perform floating point arithmetic, mastering music projects, encryption, digital signalling processing (DSP) etc.
Concurrent processing
AKA Parallel processing. Several cores working together at the same time
Co-processor
An extra processor used to supplement the CPU. Performs floating point arithmetic, graphics processing DSP etc (same as GPU)
Pipelining
Improving performance by overlapping stages of fetch execute cycle breaking down stages in arithmetic instructions etc. As soon as an instruction exits the pipeline another enters
