Computer System Architecture Flashcards
Course Related Flash Cards
Define Digital Abstraction
Simplifying the design and analysis of digital circuits by focusing on the discrete values of 0 and 1, rather than then continuous voltage levels.
Why not 1024 Registers?
Following are reasons why we don’t have 1024 registers
- Instruction Encoding become complex
- Building Cost increases
- More transistors and interconnects increasing capacitance.
- Decoding complexity increases.
- Overall Propagation Delay Increases inturn decreasing performance.
- Context Switching in OS is another issue - as register details of process needs to be saved before switching.
- Complex Compiler Optimization.
Why not Zero Registers?
If we have zero registers, the CPU will have to access memory directly every single time which will have high latency.
Why do we unsigned variants for LH and LB but not for SH and SB?
Unsigned variants are available for LH and LB because we need to identify how we are going to fill the remaining bit values in the register. We don’t need to worry about this while storing values.
Moore’s Law
The number of transistors per unit cost doubles approximately every two years.
Dennard Scaling
Power density remains constant as transistors get smaller.
Power = Capacitance x Voltage^2 x Frequency
When did Dennard Scaling end and why?
Ended in 2006. Due to the fact that the Leakage Current and Heat issues due to transisor miniaturization, making scaling of frequency impractical.
Also due to rise of multi-core systems.
Utilization Wall
Refers to the fact that even though Moore’s law allows us to add more transistors to a chip, we cannot use all of them at once due to power and thermal constraints.
What are the benefits of Digital Systems?
- They are restorative as Noise is cancelled at each digital components.
- Complex design can be constructed on the abstraction of digital behaviour.
What are the processor digital constraints?
- Chip Area
- Attainable Clock Speed.
- Instruction Level Parallelism
- Amdahl’s Law
Limitations of the processor digital constraints?
- Chip size may be smaller.
- Clock speed may be limited.
- Work per cycle may be limited.
- Benefits of more cores may be limited.
Performance Measures - What is Latency, Throughput?
Latency - Delay from when an Input enters the system until it’s associated output is produced.
Throughput - Rate at which Outputs are produced in a given time.
What are the two different type of Circuits?
Combinational Circuits and Sequential Circuits.
Combinational Circuits:
1. Contains no memory (“no state”).
2. Outputs soley depend on the inputs.
Sequential Circuit
1. Has memory (“state”)
2. Memory is updated by the output of Combinational Circuit.
What is Propagation Delay?
Maximum time it takes for a change in input to change the output.
What is Contamination Delay?
Minimum time it takes for a change in input to start changing the output.
What is Setup Time?
Time before the clock edge the input must be stable.
What is Hold Time?
Time after the clock edge the input must be stable.
What is Additive Delay?
The total of all circuit delays. This includes the extra delay from interconnects, buffering, and loading.
When can you say a good circuit has low propagation delay?
Faster Inputs
Higher Performance
What is Synchronous Sequentail Circuit?
All operations are aligned to a shared clock signal. In a Synchronous circuit, the clock period must be long enough to allow the signal to propagte through the critical path and for the state to be updated reliably.
All paths must be shorter than the clock spped.
Complex ISA can slow down the clock. Why?
Instruction length can be very complex with variable length and many different formats.
This will require more complex and time-consuming decoding logic in the CPU.
The more complex, the longer it takes, limiting how fast the CPU can complete the task.
Benefits of Pipelining
Increased throughput and Improved Hardware utilization.
Drawbacks of Pipelining
Increased Latency (however increased throughput usaully outweighs the slight increase in latency)
Increased Hardware Complexity.
Latency related Formulas
Combinational Circuit - Latency = Propagation Delay
K-Stage Pipeline - Latency = K * Clock Period
Throughput related Formulas
Combinational Circuit - Throughput = 1 / Propagation Delay
K-Stage Pipeline - Throughput = 1 / Clock Period
When does pipeline become non-deterministic?
The time a stage takes to complete varies. This can happen due to things like memory access or complex combinational logic that takes different amount of time depending on the input.
What is Elastic Pipeline?
Elastic pipelines are pipelines that dynamically adjustable pipelines that ensures correct results are provided regardless of unknown latency using mechanisms like FIFO registers and maintining equal number of pipeline registers across all stages.
Little’s Law?
L = lambda * W
L -> No of requests in the system
Lambda - Throughput
W - Latency
Von Neumann Model
All modern computers are based on the Von Neumann Model.
Components:
Main Memory - Data and Programs are held
Processing Unit - Program Counter and ALU
Storage and I/O - For communication
Classic RISC Pipeline
Fetch, Decode, Execute, Memory, and Writeback
Constraints in designing Microprocessor
- Circuit Timing
- Memory Access Latency
What is an Ill-Formed Pipeline?
Ill-Formed Pipeline states that there are inconsistency in the total number of registers used in all paths.
We have SRA, SRL, and SLL. Why is there no SLA?
SRL (Shift Right Logical) - Fills the leftmost bits with 0s, regardless of the original sign bit.
SRA (Shift Right Arithmetic) - Fills the leftmost bits with the Most Significant Bit (MSB) (preserving sign for negative numbers).
SLL is sufficient for left shifts because it already fills the least significant bits with 0s.
If an SLA were introduced, it would try to preserve the sign bit (like SRA), but this is unnecessary in left shifts leading to change of value in the register leading to incorrect results.
