Computer Structure

Question 1

Read Only Memory

Answer 1

• Used to store the bootstrap loader, which is a small piece in the operating system
• The data stored in Read Only Memory cannot be lost, it is permanent

Question 2

Random Access Memory (Notes are not there tell thomas)

Question 3

What does CPU stand for?

Answer 3

Central Processing Unit

Question 4

What does the CPU do?

Answer 4

It is the brains of the computer. It sees what data and calculations need to be carried out and then deals with how they are moved around the computer. The CPU carries out billions of instructions in one second, however, it only does one at a time.

Question 5

What are the parts of a processor

Answer 5

• Control Unit
• The Arithmetic and
  Logic Unit (ALU)
• Registers

Question 6

What do each parts of the processor do?

Answer 6

ALU - Is responsible for all arithmetic calculations and logic in the computer such as “+”, “-“.

Control Unit
- Controls the fetching, decoding and executing of program instructions
- Sends and receives control signals to and from other parts of the computer
- Connected to the ‘control’ bus

Registers
- Temporary storage locations inside the processor, they are used as they can be accessed a lot faster than locations inside of the main memory. They are use to hold data (MDR), addresses (MAR) or instructions (IR)

Question 7

What is the Structure of the CPU

Answer 7

The structure of the CPU - Consist of the processor and memory, they are connected by three ‘buses’

Question 8

Where are the programs being executed stored?

Answer 8

The main memory of the computer

Question 9

What is the order of program instructions?

Answer 9

Fetch, Decode and Execute

Freedom Dictates all Eldians

Question 10

What is MDR and MAR

Answer 10

MDR - Memory Data Register

MAR - Memory Address Register

REMEMBER - All memory locations have their unique address

Question 11

What is the Cache Memory

Answer 11

• It temporarily stores data and instructions that are used frequently
• It is slower than the registers but faster than main memory
• There are two levels of cache memory

*Level 1 Cache is built into the Processor chip
or
*Level 2 - The cache may also be built into the chip if not close it should be close to it (by it I mean the chip)

Question 12

What is the clock and clock rate?

Answer 12

The clock synchronises related components by generating pulses at a constant rate. The pulses are made to trigger components to take their next step.

The clock rate is the frequency at which the clock generates pulses.

Question 13

What is the Fetch Execute Cycle for Memory Read

Answer 13

1. MAR (Memory Address Register) sets up the address bus with the relevant memory location to be read from
2. The control unit read line is activated
3. The contents of the address held on the address bus are placed on the data bus
4. The data bus transfers the data from memory to the MDR (Memory Data Register)

Question 14

What is the Fetch Execute Cycle for Memory Write

Answer 14

1. MAR sets up the address bus with the relevant memory location to be written to
2. MDR passes the data to be written to the data bus
3. The control unit write line is activated
4. The data bus transfers the data to the memory location specified on the address bus

Question 15

What are the Factors that affect performance in computer systems?

Answer 15

The number of processors, the width of data, the cache memory and the, the clock speed

Question 16

How do these factors that affect the performance in Computer System affect
Computer systems

[IMPORTANT]

Answer 16

The number of processors:
- A dual core processor has two separate CPUs in one overall chip, likewise a quad core has four.

• The more cores a processor has, the more sets of instructions the processor can receive and process at the same time thus improving the system performance.

The width of the data:
- The larger the size of the data bus, the more data it can transfer (in one transfer)
- Therefore, the computers overall performance is improved with the more wires there are in the data bus

(FINISH THE REST)