Computer Hardware

Question 1

What is an integrated circuit

Answer 1

Millions of transistors interconnected by microscopic wires. A CPU is an example of an integrated circuit

Question 2

How are CPUs made?

Answer 2

Hundreds of copies of the same integrated circuit are etched onto a wafer of silicon. These copies are tested, and each error-free copy is cut (diced) from the wafer, and called a die. Error-free dies are mounted in a package with the die’s pads connected to the package pins.

Question 3

How do multi-core processors work?

Answer 3

Multiple independent cores (CPUs) are manufactured on the same integrated circuit

Question 4

What is Moore’s Law?

Answer 4

Transistor capacity/density doubles every 18-24 months. Power dissipation is a problem, with power required being proportional to the number of transistors switched x the frequency of switching (clock speed)

Question 5

If we are given a function f(x0, x1, x2, …, xN) : {0, 1}^n => {0, 1}^m, then…

Answer 5

We can build a circuit that computes f using only AND, OR and NOT gates

Question 6

What does the datapath on a processor do?

Answer 6

Performs data processing operations
Includes the arithmetic logic unit, and registers

Question 7

What does the control part of a processor do?

Answer 7

Tells the datapath, memory and I/O devices what to do

Question 8

What is the cache?

Answer 8

Small, fast, relatively expensive on-chip memory

Question 9

What is the von Neumann architecture?

Answer 9

It means that the program and its data both share the same memory (e.g. Little Man Computer), allowing for self-modifying programs

Question 10

What is the von Neumann bottleneck?

Answer 10

The limitation of the data transfer rate between the CPU and memory. It led to the use of cache

Question 11

What is the Harvard architecture?

Answer 11

Instruction memory and data memory are separated, each with their own buses, doubling data bandwidth

Question 12

What does memory consist of?

Answer 12

Pigeon-holes containing data, each holding 8 bits and having a unique address

Question 13

Address bus

Answer 13

Carries an address, width determines size of addressable memory

Question 14

Data bus

Answer 14

Carries contents of memory, width determines the word size

Question 15

Control bus

Answer 15

Deals with information transfer, specifies whether data is being read or written, signals to input/output devices

Question 16

External storage, RAM, cache

Answer 16

External storage: cheap, slow, far from the CPU
RAM: Each bit is stored by a capacitor, somewhat slow and cheap, must be refreshed by the memory controller
Cache: expensive, fast, split into Level 1 (small, fast, in the CPU) and Level 2 (slightly larger and slower, either in the CPU or a short distance away), and Level 3. These need to be refreshed

Question 17

CPU manufacturing process

Answer 17

Start with a silicon ingot
Slicer turns it into thin wafers
Etch the IC onto the wafers
Test the wafers to determine which parts are defective
Dice the wafers up and throw away the dies previously found to be defective
Bond die to package
Packaged dies
Part tester
Tested packaged dies

Question 18

What do we use transistors for?

Answer 18

Building gates which take binary inputs (voltage/no voltage) and produce binary outputs

Question 19

Describe a half-adder

Answer 19

Output: Sum = (A OR B) AND NOT(A AND B) = A XOR B
Output: Carry = A AND B
1+1 = 0 with carry
Carry + 0 + 0 = 1
Carry + anything else = results in carry

Question 20

Describe an adder

Answer 20

Made up of two half-adders
Overall input: A, B, Carry in
First adder input: A, B
First adder output: S1, C1
Second adder input: Carry, S1
Output: S2, (C1 OR C2)

Question 21

What is the modified Harvard architecture?

Answer 21

CPU cache is separated into data cache and instruction cache, with more space for data. Before, data was kicking instructions out.

Question 22

FETCH, decode, fetch, execute (instruction fetch)

Answer 22

CPU sends value of Program Counter to Address Bus
Memory puts contents at this memory address on the data bus
Instruction is stored in the CPU’s Instruction Registers

Question 23

fetch, DECODE, fetch, execute

Answer 23

The instruction word in the Instruction Registers is decoded by internal logic to provide control signals to ALU and other internal circuits inside the CPU
Program counter value pushed onto Address Bus, the ALU picks it up, increments it by the word size and puts it back into the Program Counter

Question 24

fetch, decode, FETCH, execute (operand fetch)

Answer 24

The instruction registers send the address of the data to be processed (operand address), to the address bus
Memory supplies the operand data to the data bus, and it goes to the ALU ready for processing

Question 25

fetch, decode, fetch, EXECUTE

Answer 25

The ALU processes the operand according to the instruction and puts the result in the accumulator
The program counter might need to be updated, if it was a jump instruction
The result from the accumulator might have to be written back into memory

Question 26

What is the Instruction Set Architecture?

Answer 26

The interface between hardware and software, the view the programmer has of hardware
Includes everything programmers need to know to program the processor

Question 27

What does the ISA include?

Answer 27

Structure of programmable storage (memory)
Instruction sets for using the processor
Modes of addressing and accessing data items within memory
Process of execution (FDFE)
A primary component is its assembly language (very low-level and goes on to be implemented as machine code)

Question 28

Describe MIPS

Answer 28

4GB memory, 32 bit address bus, 4 byte words, 32-bit registers $zero $s1 $s2 etc.
When we request the contents of a memory address m, we get the contents of m, m+1, m+2 and m+3

Question 29

I-type instructions

Answer 29

6-bit opcode (instruction code)
5-bit source register (Rs)
5-bit destination register (Rd)
16-bit memory address or constant (use offsets and indirect addressing)
e.g. addi $s3, $s3, 1 =
001000 10011 10011 0000000000000001

Question 30

R-type instructions

Answer 30

6-bit opcode
two 5-bit source registers (Rs1 and Rs2)
5-bit destination register (Rd)
5-bit shift amount for shift instructions
6-bit funct (supplement for opcode in some instructions)
e.g.
slt $s6, $s1, $s5

Question 31

J-type instructions

Answer 31

6-bit opcode
26-bit address to jump to
e.g.
j 8

Question 32

Process of compiling and executing source code

Answer 32

Source code => compilation/translation => assembly/bytecode => machine code => voltages

Question 33

Main functions of an operating system

Answer 33

Interface between applications and hardware
Virtualisation: you don’t have to manage specific memory addresses of variables or the exact location of a file on the disk, the OS abstracts it away and deals with it for you
Manages memory and the starting/stopping of programs (frees memory when a program is closed) and time slicing
Handles input/output (interrupts)

Question 34

What is a bus?

Answer 34

Lines of communication (physical wires)
Cheap and versatile but very slow, causing bottlenecks

Question 35

What is an interrupt?

Answer 35

When a device wants to send input, it raises an interrupt on a bus line, which is a request for the CPU to interrupt currently executing code and process the input. Dealt with by the interrupt handler

Question 36

What is a process?

Answer 36

A program in execution (a thread + address space/allocated memory)
A thread is a sequence of instructions in memory

Question 37

What is mutual exclusion?

Answer 37

When the OS prevents two different threads from accessing the same memory location
Each thread has to ask the OS for permission to access c (critical section)

Question 38

List the different process states

Answer 38

new: Process being created
ready: Not on CPU, but ready to run
running: executing on CPU
blocked: waiting for an event (usually I/O)
exit: process finished

Question 39

List the different process state transitions

Answer 39

admit: process control set up, move to run queue (new => ready)
dispatch: scheduler gives CPU time a process which is ready
timeout/yield: running process gives up CPU time and becomes ready
event-wait: process waiting for event gives up CPU time and becomes blocked
event: event occurs, process goes from blocked to ready
release: process terminates, resources can be released

Question 40

Process control block

Answer 40

A data structure used by the kernel to manage a process:
- Unique process ID
- Process state
- CPU scheduling information: priority, events pending
- Location of address space
- When the process was last run, CPU time lapsed
When not running: program counter, values in other CPU registers

Question 40

What is a context switch?

Answer 40

Switching between two different processes (moving from ready to running)
Process A saves state into PCB A and becomes ready
Process B restores old state from PCB B and becomes running

Question 41

What is the current trend in microprocessor design so as to overcome difficulties with power dissipation as we build faster and faster single processors?

Answer 41

Multi-core processors where one CPU with a high clock-speed is replaced with a number of CPUs with lower clock-speeds but which, when working together, can give better computational power.