Computer Architecture Flashcards
Fill in the blank: A memory unit in Von Neumann Architecture stores _______.
data and instructions
What is pipelining in processor architecture?
Overlapping operations to improve efficiency
What problem occurs in in-order pipelines?
Pipeline stall / Execution Bubble
What are the types of instruction dependences?
- Read after Write (RAW)
- Write after Read (WAR)
- Write after Write (WAW)
What is out-of-order execution?
Allows instructions to be executed in a different order than they appear in the program to maximize resource utilization
What is the role of the Branch Prediction Unit (BPU)?
Tracks branch addresses and their statuses in a BTB (Branch Target Buffer) structure
What is the difference between a single and double bit branch predictor?
Double bit branch predictor takes last 2 predictions into account (vs. last) and changes prediction in case of 2 mispredictions (vs. 1).
Name 3 static branch predictions
if => not taken
for => taken
call / return => taken
What does SIMD stand for?
Single Instruction, Multiple Data
What is the purpose of SIMD execution?
To execute the same operation on multiple data elements
List the types of data supported by SIMD instruction sets.
- 8x long
- 16x int
- 32x short
- 64x char
What is a fused instruction in SIMD?
Combines two operations, such as multiply and add
What is the main advantage of superscalar execution?
Parallely executing different instructions or the same instruction on different data
What does Simultaneous Multi-Threading (SMT) aim to achieve?
Feed multiple instruction streams into execution units
What is the function of a Reorder Buffer in out-of-order execution?
Restores original instruction order before committing results
What is the effect of a pipeline bubble?
Pipeline stalls until the long operation is finished
What is an example of a dynamic branch predictor?
2-bit predictor (saturating counter)
Fill in the blank: In SIMD, load and store operations transfer data from _______ to registers.
memory/caches
What does the term ‘out-of-order pipelining’ refer to?
Exploiting instruction independence in a linear stream
How does branch prediction impact performance in pipelines?
Reduces stalls caused by conditional branches
What is the purpose of the instruction ‘vaddpd’?
To perform a vector addition of packed double-precision floating-point elements
‘vaddpd’ stands for Vector Add Packed Double-Precision Floating-Point.
What does ‘Fused Instructions’ refer to?
Two operations fused into one SIMD instruction
Example: multiply and add operations.
What is the significance of the number ‘256’ in the context of SIMD instructions?
It indicates the width of the SIMD instructions in bits
This often relates to the data that can be processed simultaneously.
What is the function of the ‘vfmadd213ps’ instruction?
It computes fused multiply-add of packed single-precision floating-point elements
This instruction performs multiplication followed by addition in one step.
What does ‘Conditional Evaluation’ mean in SIMD instructions?
It limits the effect of instructions to a subset of SIMD elements using a mask register
This allows selective processing of data.
Fill in the blank: The instruction ‘vbroadcast’ is used to _______.
[assign a scalar value to all SIMD elements]
What is the purpose of shuffle and swizzle instructions in SIMD?
To modify data layout in the SIMD register
Examples include separating real and imaginary parts of complex numbers.
What does ‘vpermilpd’ do?
It permutes packed double-precision floating-point elements within a single operand
This instruction allows for specific reordering of data elements.
What is the role of ‘vperm2f128’?
To permute 128-bit chunks from two source operands into a destination
This is useful for rearranging data in SIMD processing.
What is the meaning of ‘Non-uniform memory access’ in the context of processor architecture?
It refers to memory access times that vary based on the memory location relative to the processor
This affects performance and efficiency in memory-intensive applications.
How does branch prediction help?
helps avoid pipeline stalls by speculating the correct execution path and determining in advance which instruction should be fetched next
What are the 2 locality principles of caches?
Temporal Locality: data items accessed will be accessed again in the future
Spacial Locality: data items accessed are close to each other
What is the difference between inclusive and non-inclusive cache?
Inclusive caches keep copy of a cache line in each level
Non-inclusive caches evict higher cache levels copy
Name 2 cache issues
Compulsory Cache Miss (initial access to data will always be a miss)
Capacity Cache Miss (data evicted before it can be reused because too large for the cache)
Which effect do memory fences have?
re-ordering of mem operations in the out-of-order engine is restricted
What should be considered when using a shared variable among threads given a relaxed consistency model?
OOO execution might rearrange load and store operations depending on the memory consistency model
What is snoop filtering?
Snoop filtering reduces unnecessary coherence traffic by tracking which cache lines are present in each core’s cache, preventing redundant snoop requests when a cache miss occurs
