Computer architecture Flashcards

1
Q

What is the average annual growth in processor performance prior to the mid-1980s?

A

22% per year, doubling performance every 3.5 years

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2
Q

What architectural ideas contributed to the increase in growth to about 52% starting in 1986?

A

More advanced architectural and organizational ideas typified in RISC architectures

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3
Q

What happened to uniprocessor performance from 2003 until 2011?

A

Slowed to 23% per year

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4
Q

What was the annual improvement in processor performance from 2011 to 2015?

A

Less than 12%, doubling every 8 years

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5
Q

What is the annual improvement in processor performance since 2015?

A

3.5% per year, doubling every 20 years

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6
Q

What is the performance-centric design approach in computing architectures?

A

Focus on tools and techniques like shared memory architecture, cache memory hierarchy, pipelined execution, and more

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7
Q

What are the classes of computers classified by functionality?

A
  • Personal Mobile Devices (PMDs)
  • Desktop computers
  • Servers
  • Cluster/warehouse scale computers
  • Embedded computers
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8
Q

What are the key features of servers in computing?

A
  • Availability
  • Scalability
  • Throughput
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9
Q

What is Flynn’s Taxonomy?

A

A classification proposed by Micheal Flynn in 1966 based on instruction and data streams

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10
Q

What are the four classes of Flynn’s Taxonomy?

A
  • Single instruction stream, single data stream (SISD)
  • Single instruction stream, multiple data streams (SIMD)
  • Multiple instruction streams, single data stream (MISD)
  • Multiple instruction streams, multiple data streams (MIMD)
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11
Q

What does RISC stand for?

A

Reduced Instruction Set Computing

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12
Q

What is a key characteristic of RISC architecture?

A

Small and simple instruction set

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13
Q

What does CISC stand for?

A

Complex Instruction Set Computing

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14
Q

Fill in the blank: RISC architecture reduces the cycles per instruction while ______ architecture reduces the number of instructions per program.

A

CISC

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15
Q

What is the main execution cycle characteristic of RISC?

A

Single-cycle execution

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16
Q

What is meant by ‘Load/Store Architecture’ in RISC?

A

Only load and store instructions can access memory; all other instructions operate on registers

17
Q

What is a significant advantage of having a large number of registers in RISC?

A

Reduces the need to access slower main memory

18
Q

What does pipelining refer to in RISC architecture?

A

A technique that allows multiple instructions to be processed simultaneously at different stages

19
Q

List three common characteristics of RISC.

A
  • Small instruction set
  • Large number of registers
  • High instruction throughput
20
Q

What is the significance of compiler optimization in RISC architecture?

A

RISC relies heavily on optimizing compilers to generate efficient code

21
Q

True or False: RISC architectures typically avoid complex, specialized instructions.

22
Q

What are some examples of RISC architectures?

A
  • ARM
  • MIPS
  • SPARC
  • PowerPC
23
Q

What is the primary goal of RISC architecture in terms of instruction execution?

A

Optimized for speed

24
Q

What does RISC stand for?

A

Reduced Instruction Set Computer

RISC architectures focus on a small set of simple instructions.

25
What is a common characteristic of RISC architectures?
Small Instruction Set ## Footnote RISC architectures have fewer instructions compared to CISC architectures.
26
What is meant by Single-Cycle Execution in RISC?
Most instructions complete in one clock cycle ## Footnote This characteristic allows for faster execution of instructions.
27
What is Load/Store Architecture?
Only load/store instructions access memory; other instructions operate on registers ## Footnote This approach minimizes memory access and enhances performance.
28
What is the significance of a Large Register Set in RISC?
Many general-purpose registers to minimize memory access ## Footnote The abundance of registers reduces the need to access slower memory.
29
How does Efficient Pipelining benefit RISC architectures?
Instructions are optimized for pipelining, allowing high throughput ## Footnote Pipelining enables multiple instruction phases to occur simultaneously.
30
Describe Simple Addressing Modes in RISC.
Limited and straightforward memory addressing modes ## Footnote Simplicity in addressing makes instruction execution faster and easier.
31
What role do compilers play in RISC architectures?
Relies on compilers for efficient instruction scheduling and optimization ## Footnote Compilers optimize the use of available instructions and registers.
32
What is the function of Microcode in RISC?
Executes instructions directly in hardware without needing microcode ## Footnote This reduces the complexity and overhead of instruction execution.
33
How does High Instruction Throughput affect RISC performance?
High-speed instruction execution due to pipelining and load/store architecture ## Footnote This characteristic allows RISC processors to handle more instructions in a given time.
34
What is the benefit of a Uniform Instruction Format in RISC?
Fixed-length instructions make decoding simpler and faster ## Footnote Uniformity in instruction length enhances the efficiency of the CPU's instruction decoding process.
35
True or False: RISC architectures typically have more complex instructions than CISC architectures.
False ## Footnote RISC architectures focus on a smaller set of simpler instructions.
36
Fill in the blank: RISC architectures are characterized by _______.
[a small instruction set] ## Footnote This characteristic is fundamental to the RISC design philosophy.