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Computer Systems > Computer Architecture > Flashcards

Computer Architecture Flashcards

1
Q

What is a clock?

A

A clock drives the steps in the processor - everything happens on the clock “edge” as systems are synchronous

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2
Q

What does the Program Counter do?

A

Contains the address of the instruction to run
Increments after each instruction

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3
Q

What does the Instruction Register do?

A

Contains the instruction most recently fetched

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4
Q

What does the Memory address register do

A

Contains the address of a location in memory

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5
Q

What does the Memory buffer register do?

A

Contains a word of data to be written to memory or the word most recently read

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6
Q

What happens in the fetch part of the fetch-execute cycle?

A
  • PC contains address of next instruction
  • Address moved to MAR
  • Address placed on address bus
  • Control unit request memory read
  • Result placed on data bus, copied to MBR, then to IR
  • PC incremented by 1
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7
Q

What happens in an indirect fetch cycle?

A

it fetches the data stored in the memory location, to use the data to fetch/reach the memory location of the data required

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8
Q

Advantages of Von Neumann?

A

Simple - data and instructions stored in a single memory space
Cost-Effective - Smaller number of components

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9
Q

Disadvantages of Von Neumann

A

Bottleneck - Shared bus, simultaneous obtaining impossible
Memory Corruption - same memory space, erase

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10
Q

Advantages of Harvard

A

Faster processing - Two buses
Improved Security - Not stored in same location, no erase
Efficient use of resources

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11
Q

Disadvantages of Harvard

A

Complexity - intricate design
Higher cost
Less Flexibility

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12
Q

RISC characteristics

A
  • Instructions of fixed length in a single clock cycle
  • Pipelines to achieve one-instruction-per-one-clock-cycle
  • Simple control logic to increase clock speed
  • Operations performed on internal registers (load store instructions access external memory only)
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13
Q

CISC characteristics

A
  • Binary compatibility (old binary code on newer systems)
  • Complex control logic
  • Use of micro-code
  • Variable length instructions to save program memory
  • Small internal register sets compared with RISC
  • Complex addressing modes, operands can reside in external memory or internal registers
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14
Q

What is pipelining?

A

Pipelines overlap operations to aim to complete an instruction every clock cycle

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15
Q

What are the different ways of branch prediciton?

A
  • Multiple streams
  • Prefetch Branch Target
  • Loop buffer
  • Branch prediction
  • Delayed branching
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16
Q

How does multiple streams work in pipelining?

A
  • Have two pipelines
  • Prefetch each branch into a separate, appropriate pipeline
  • Waste the branch you didn’t need
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17
Q

Disadvantages of Multiple streams

A
  • Leads to bus & register
  • Multiple branches lead to further pipelines being needed
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18
Q

How does Prefetch Branch Target work?

A
  • Target of branch is prefetched in addiction to instructions following branch
  • Keep target until branch is executed
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19
Q

How does Loop Buffer work?

A
  • Stores all the instructions of a loop in a buffer in the CPU
  • Optimises the process of jumping away from the previous instruction
  • Check buffer before fetching from memory
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20
Q

How does Static Branch Prediction work?

A
  • Predicts one side (jump or not jump)
  • If no jump, always fetch next instruction
    -If jump, fetch target instruction
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21
Q

How would Branch Predicition be improved?

A
  • Predict using the opcode
  • Produce Statistics related to the likely hood of jumping
  • Can learn
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22
Q

What is a superscalar processor?

A

A processor that completes more than one instruction per clock cycle

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23
Q

What is In-Order Issue, Completion?

A
  • Issue instructions in the order they occur
  • May fetch >1 instruction
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24
Q

Disadvantages of In-order Issue, Completion

A
  • Not very efficient
  • Instructions must stall if necessary
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25
Q

What is True Data Dependency?

A

It can execute fetch and decode two instructions simultaneously but not execute the second because it is dependent on the first

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26
Q

What is Procedural Dependency?

A

Can not execute instructions after a branch in parallel with instructions before a branch, preventing simultaneous fetches

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27
Q

What is Resource Conflict?

A

Two or more instructions requiring access to the same resource at the same time

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28
Q

What is Out-of-Order Issue, Completion?

A
  • Decouple decode pipeline from execution pipeline
  • Can continue to fetch and decode until this pipeline is full
  • When a functional unit becomes available, an instruction can be executed
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29
Q

What is an Antidependency?

A

A register value is needed but changed in the next instruction

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30
Q

What is an Instruction Set?

A

The structure of a computer that a machine language programmer must understand to write a correct program for that machine

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31
Q

What is opcode?

A

The operation code is the instruction/task that has to be completed

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32
Q

What is the operand reference?

A

Where the data is referenced, the item of data is used from there

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33
Q

What is the result reference?

A

Where the instruction output gets put

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34
Q

What does the ALU do?

A

It does the arithmetic and logic operations in the CPU. It can also shift or rotate bits

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35
Q

What is the benefit of more addresses per instruction?

A
  • More complex (powerful?) instructions
  • More registers
  • Register-to-Register operations are quicker
  • Fewer instructions per program
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36
Q

What is the benefit of fewer addresses per instruction?

A
  • Less complex instructions
  • More instructions per program
  • Faster fetch/execution of instructions
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37
Q

What is the important of data alignment?

A

Reading miss-aligned data may need multiple memory reads and shift which will negatively effect performance

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38
Q

What is Endianness

A

How are bytes in a word ordered and how are bits in a byte ordered

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39
Q

How are bytes ordered in big endian?

A

Most significant byte in the lowest numerical address

40
Q

How are bytes stored in little endian?

A

The least significant byte in the lowest numerical address

41
Q

What are characteristics of big endian?

A
  • Memory dumps left to right (easy for western audiences)
  • Big endian machines store character strings and integers in the same order
  • Has to perform an extra operation (addition) when converting from 32 to 16 bit address
42
Q

What is the main 5 instruction set architectures?

A
  • Accumulator based
  • Stack based
  • Register-memory based
  • Register-register
  • Memory-Memory
43
Q

How does Accumulator ISA work?

A

A value is loaded into the accumulator and another is added directly from memory with the result stored in accumulator

44
Q

How does Stack based ISA work?

A
  • Both operands pushed onto the stack
  • The result is popped off the stack
45
Q

How does Register-memory ISA work?

A
  • One input is loaded from memory
  • It gets added to by a value put into a register and the result is stored in a register

LOAD R3, A
ADD R1, R3, B
STORE R1, X

46
Q

How does Register-Register ISA work?

A
  • Operands are loaded from memory to registers
  • Add uses the operands stored in registers
47
Q

Advantages of Accumulator ISA

A
  • Short Instructions
  • One implicit operand, one explicit
48
Q

Disadvantages of Accumulator ISA

A
  • Single temporary storage location
  • High memory traffic
49
Q

Advantages of Stack ISA

A
  • Simple model
  • Short instructions
  • Implicit operands
50
Q

Disadvantages of Stack ISA

A
  • The stack cannot be randomly accessed
  • Stack becomes a bottleneck
51
Q

Advantages of Register ISA

A
  • Easy code generation
  • Clever compiler optimisations
  • Fast access to temporary values
52
Q

Disadvantages of Register ISA

A
  • Operands must be named
  • Longer instructions
53
Q

Advantages of Register-Memory

A
  • Simple code generation
  • Data can be accessed directly
54
Q

Disadvantages of Register-Memory

A
  • Functionally commutative operations, non-commutative behaviour
  • Instructions require a variable number of cycles
55
Q

Advantages of Register-Register

A
  • Fixed-size instructions
  • Simple code generation
  • (Most) instructions require a similar, known number of cycles
  • Fast
56
Q

Disadvantages of Register-Register

A

High instruction count

57
Q

Advantages of Memory-Memory

A

Produces compact code

58
Q

Disadvantages of Memory-Memory

A
  • Large variation in instruction size
  • Large variation in execution time per instruction
  • Memory access is the bottle neck
    No longer used
59
Q

What is Memory Connection?

A
  • Consists of N words of equal length with unique address
  • Memory receives addresses and receives control signals (Read, Write, Timing) and sends data
60
Q

What is a CPU connection

A
  • Reads instruction and data
  • Sends control signals to other units
  • Receives and acts on interrupts
61
Q

What is a shared bus?

A

A common communication pathway

62
Q

What does the address bus do?

A

Identify the source or destination of data

63
Q

What does the Control bus do?

A

Control and timing of information

64
Q

What are the typical control lines?

A
  • Memory read/write signal
  • I/O Port read/write signal
  • Transfer Acknowledgement
  • Bus request/grant
  • Interrupt request/acknowledgement
  • Clock signals
  • Reset
65
Q

What issues are caused by a single bus?

A
  • Propagation delays, different devices may work at different speeds
66
Q

Why is Timing import with interconnects and buses?

A
  • Coordination of events on bus
  • Normally Synchronous as events are determined by clock signals
67
Q

What is the PCIe (Peripheral Component Interconnection express)?

A

A serial bus with multi- GiByte/s “lanes” where the speed depends on the version. it uses more lanes for a GPU card

68
Q

How does a module use a bus?

A
  • Obtain the use of the bus
  • Transfer data and/or requests
  • Synchronise and/or acknowledge
69
Q

What does the PCIe do?

A

High-speed serial computer expansion bus standard. It is like a network with layers and addressing

70
Q

What is SAS (Serial attached SCSI)?

A
  • Very fast serial SCSI, compatible with latest SATA
  • Very flexible due to the layers of the protocol
71
Q

What are characteristics of a USB?

A
  • Ideal for low-speed to high I/O devices
  • Expandable as it is simple design and configuration that allows up to 127 devices
72
Q

What are the elements of a USB’s hardware?

A
  • Assumes a root hub connected to the main bus
  • Cable contains four wires
  • Data transmitted as 0 for a voltage transition and 1 as the absence of one
73
Q

What are the four kind of USB frame signals?

A
  • Control
  • Isochronous (For real time devices where data should be sent/received at precise intervals)
  • Bulk
  • Interrupts (Used for regular polling of devices)
74
Q

What do motherboard interconnects do?

A
  • High speed links to chipset from one or more CPU packages
  • Links are very similar to PCIe
75
Q

What is a chiplet?

A

Putting lots of chips together

76
Q

What is a chipset?

A

A set of electronic components on one or more integrated circuits that manages data flow

77
Q

What is UPI (UltraPath Interconnect)

A
  • Intel’s proprietary high speed link
  • Point to point link between CPU chips and to chipset
  • Handles cache-coherency
  • Around 20GiB/s per link
78
Q

What is BIOS (basic input/output system)?

A
  • Firmware on the motherboard
  • Hardware initialisation
  • Booting
79
Q

Where is BIOS stored?

A

In Flash memory

79
Q

What does BIOS do?

A
  • Used for I/O functions in MS-DOS to help standardise PCs
  • finds a boot loader on disk/CD/USB
  • Loads first sector of disk into RAM
80
Q

What is UEFI (Unified Extensible Firmware Interface) ?

A

Replaces old BIOS and connects a OS to its firmware

81
Q

What is Flynn’s Taxonomy?

A

Classification of computer architectures

82
Q

What is SISD?

A

Single Instruction Single Data

83
Q

What is MISD?

A

Multiple Instruction Single Data

84
Q

What is SIMD?

A

Single Instruction Multiple Data

85
Q

What is MIMD?

A

Multiple Instruction Multiple Data

86
Q

What does SIMD need?

A

Special hardware i.e. Streaming SIMD Extensions and special software

87
Q

What is SSE used for?

A
  • Image processing
  • Video processing
    -array/vector processing
  • text processing
  • General speed-up
88
Q

What is SIMD used for?

A

Cuda and GPU processing

89
Q

What is SMP (Symmetric Multiprocessors)?

A
  • A MIMD System that has multiple CPUs share main memory and I/O
  • The hardware manages contention and increases the performance especially multiuser/thread
90
Q

How does a Typical SMP system work?

A
  • Each processor has its own L1 and L2 cache
  • Connected by a system bus, crossbar switch or other interconnect
  • Main memory, I/O, etc are also connected to the interconnect
91
Q

What is Heterogenous Multi-processing?

A
  • Combine big performance cores with little energy efficient cores
  • “Big” cores only used when performance is necessary, “little” cores used for most tasks
  • Needs operating system support to fully leverage
92
Q

What is Simultaneous multithreading (SMT) / Hyper-threading?

A
  • Hardware multi-threading on superscalar CPUs
  • Executes multiple instructions at the same time using redundant execution units in the processor
93
Q

What is Data parallelism?

A

Split the data to make independent parallel tasks

94
Q
A

Computer Systems (6 decks)

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