Computer architecture Flashcards
What is a chipset
a set of electronic components in an integrated circuit known as a “Data Flow Management System” that manages the data flow between the processor, memory and peripherals
Examples of peripherals
Disk drive, keyboard, monitor, solid state drive
Xeon chipsets contain what two things?
Memory controller hub and I/O controller hub
Memory controller hub is aka
North bridge
IO controller hub is aka
South brdge
Bus
is a communication system that transfers data between components inside a computer, or between computers. This expression covers all related hardware components (wire, optical fiber, etc.) and software, including communication protocols.[3]
Local bus
a computer bus that connects directly, or almost directly, from the central processing unit (CPU) to one or more slots on the expansion bus.
What does RAM require?
A constant power supply, since it is a volatile form of memory
DIMM stands for
Dual Inline Memory Module
DIMM
The physical part of a computer the RAM is in
Relationship between DDR, RAM, and DIMM
DDR is a type of RAM stored on a DIMM
What does a DIMM look like?
[upload image]
DRAM consists of
A transistor and a capacitor that create a memory cell, which represents a single bit
IPC
Instructions per clock
SMT stands for
Simultaneous multithreading
TLB stands for
Translation Lookaside Buffer
TLB
a memory cache that is used to reduce the time taken to access a user memory location
A TLB is part of what?
The chip’s MMU (memory management unit)
Why can a TLB miss be more expensive than a instruction cache miss or data cache miss?
Bc of the need for not just a load from main memory, but a page walk, requiring several memory accesses
A CPU has to access memory in what 3 scenarios?
A data-cache miss, an instruction-cache miss, or a TLB miss
When does a TLB miss happen?
the desired information itself actually is in a cache, but the information for virtual-to-physical translation is not in a TLB
Cache lines are aka
Cache blocks
Cache lines
The blocks of fixed size that data is transferred between memory and cache in. Almost always are multiples of 64 bytes, in the sense that a request for a certain byte gets mapped to the block address formed by ignoring the last 6 bits of the address
What is significance of TLB cache being part of MMU?
The TLB is not related directly to the CPU caches
Pre 2010 hard disk sector size
512 bytes
Post 2010 typical hard disk sector size
4096 bytes
