Computer Arch Flashcards
Understanding arithmetic and logical operations with integer operands, floating-point number systems and operations.
Computer Architecture
instructions cycles: …,….
Fetch Cycle
Execute Cycle
Contains the 8-bit op-code instruction being executed.
Instruction Register (IR)
It deals with functional behavior of computer system
Computer Architecture
the father of all modern computers
IAS
Architecture describes …… the computer does
What
…….,……computers were examples of first-generation computing devices.
The UNIVAC and ENIAC
the operational units and their interconnection that realize the architecture specification.
Computer Organization
helps plan the selection of a processor for a particular project
Computer organization
…..carried out the four basic arithmetic operations and perhaps higher arithmetical functions
such as roots, logarithms, trigonometric functions, and their inverses
Central Arithmetical unit (CA)
in IAS . Each register has….bits
40
ENIAC, Addition and subtraction were performed with …. accumulators
20
Using Computer organization computer programs performance could be……..
optimized
….. control the proper sequencing of operations and make the individual units act together to carry out the specific task programmed into the system(EDVAC)
Central Control Unit (CU)
Computer Architecture deals with …….. behavior of computer system
functional
Computer organization deals with ……relationship
structural
Contains the word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the 1/0 unit.
Memory Buffer Register (MBR)
Understanding the concept of programs as sequences of machine instructions.
Computer Architecture
Multiplier Quotient (MQ)
Employed to hold temporarily operands, results of ALU operations, the least- significant bits of the product as multiplication proceeds, and the quotient from division.
The first computers ever used ……. for circuitry and …….for memory
vacuum tubes, magnetic drums
To give a basis understanding of computer operations, roles of processors, main memory, and input/output devices.
Computer Architecture
……..Involves logic
Arch
It comes before Computer organization while designing a computer
Computer Architecture
performed when the op-code is in IR. The Control circuitry send out the appropriate control signals to cause data to be moved or an operation to be performed by the ALU.
Execute Cycle
……a metal cylinder coated with magnetic iron-oxide material on which data and programs can be stored
A magnetic drum
Understanding memory organization, including cache structures and virtual memory schemes.
Computer Architecture
The IAS operates through performing an …… which consists of ….. sub- cycles.
instructions cycle epetitively ,two
The IAS machine language instructions are ….bits long
20
the op-code of the next instruction is loaded into the IR and the address is loaded into the MAR. This instruction may be taken from the IBR, or it can be obtained from memory by loading a word into the MBR, and then down to the IBR, IR, and MAR.
Fetch Cycle
Contains the address of the next instruction-pair to be fetched from memory.
Program Counter (PC)
Interface between hardware and software
arch
The EDVAC was organized for 4 main parts
Central Arithmetical unit (CA)
Central Control unit (CU)
Memory (M)
Input/Output devices (I/O).
each addressable word in memory contains …..
40 bits
op-code memory- address, where op-code is an …. operation code and memory-address is a …. memory address.
8-bit, 12-bit
Understanding the relationship between assembly language and machine language.
Computer Architecture
….. units were the interface between computer and user.
I/O
organization describes…. it does it
How
……store both numerical data (variables, constant,…) and instructions.
Memory
a set of disciplines that describes a computer system by specifying its parts and their relations.
Computer Architecture
Employed to hold temporarily the right-hand instruction from a word in memory
Instruction Buffer Register (IBR)
first computers which stored both the program and the data in the computer’s memory
IAS
Specifies the address in memory of the word to be written from or read into the IVIBR.
Memory Address Register (MAR)
called Selectron that has up to 1024 (40-bit memory locations) words. There are also several other registers that are used internally by the computer but are invisible to the machine- language programmer. (IAS)
Memory (RAM)
…. involves Physical components
organization
Architecture and organization are ……..
independent
Holds the output of the ALU after an arithmetic operation, a temporarily operands loaded from memory, the most-significant digits of a product, and the divisor for division.
Accumulator (AC)
included some 18,000 vacuum tubes and 1,500 relays.
ENIAC
The IAS has an …..
accumulator register, AC, and an arithmetic register, AR
replaced vacuum tubes
Transistors
a device composed of semiconductor material that amplifies a signal or opens or closes a circuit.
Transistor
Transistors were miniaturized and placed on silicon chips, called ……
semiconductors
……. is a small piece of semi conducting material on which an
integrated circuit is embedded.
A chip
control the logic of almost all digital devices, from clock radios to fuel- injection systems for automobiles.
Microprocessors
The number of bits processed in a single instruction.
Bandwidth
Given in megahertz (MHz), the ……. determines how many instructions per second the processor can execute.
Clock Speed
The set of instructions that the microprocessor can execute.
Instruction Set
combines the ALU and the control unit into one functional unit
CPU
one device can be a bus master, and the remaining devices are then considered to be slaves. The master controls the bus, and can be either a ……or……
sender, a receiver.
it contains a clock (CLK) that sends out a sequence of 1’s and 0’s at timed intervals.
Synchronous
clock (CLK) sends out a sequence of …….. at timed intervals.
1’s and 0’s
………. is used to synchronize bus operations
The clock signal
This bus clock is generally derived from the ……..
master system clock
Causes data on the bus to be written into the addressed location
Memory write
Causes data from the addressed location to be placed on the bus
Memory read
Causes data from the addressed I/O port to be placed on the bus
I/O read
Causes data on the bus to be output to the addressed I/O port
I/O write
I/O write
Causes data on the bus to be output to the addressed I/O port
Indicates that data have been accepted from or placed on the bus
Transfer ACK
Indicates that a module needs to gain control of the bus
Bus request
Indicates that a requesting module has been granted control of the bus
Bus grant
indicates that an interrupt is pending
Interrupt request
Acknowledges that the pending interrupt has been recognized
Interrupt ACK
Initializes all modules
Reset
Is used to synchronize operations
Clock
for electrical power to the components, which is not shown, but its presence is understood.
Power Bus
ISA is a short for ………. and ISA was introduced by …….
Industry Standard Architecture ,IBM.
identifies where the information is being sent (bus)
Address Bus
Address Bus connections between
the microprocessor and memory
carries the information being transmitted
Data Bus
The number of wires used in the data bus
width
describes aspects of how the information is being sent, and in what manner.
Control Bus
connections between
(Control Bus)
CU , CPU
Data Bus are
Bi-directional
Data Bus exchange data between
processor , Memory ,peripherals
PCI was introduced by
Intel
a 32-bit computer bus that is also available as a 64-bit bus running at 66 MHz providing up to 528 MB/sec bandwidth, -while the data and address lines are multiplexed.
The PCI
PCI is a computer bus for attaching ……
hardware devices in a computer
many tasks traditionally performed by expansion cards may now be performed equally well, by ….. devices.(PCI Bus)
USB
The original release of USB supports 127 devices transferring 12 Mbps.
USB 1.0
full-speed USB
USB 1.1
hi-speed USB
USB 2.0
supports 12 Mbps
USB 1.0 , USB 1.1
