Computational Pipelining Flashcards
Q: What is pipelining in computer architecture?
A: An implementation technique where multiple instruction stages are overlapped to improve throughput.
Q: Does pipelining improve individual instruction latency?
A: No — it increases instruction throughput, not individual instruction speed.
Q: What are the 5 classic pipeline stages?
A: 1) Instruction Fetch (IF),
2) Instruction Decode (ID),
3) Execute (EX),
4) Memory Access (MEM),
5) Write Back (WB).
Q: What is the ideal CPI (Cycles Per Instruction) in a perfect pipeline?
A: CPI = 1.
Q: What limits the performance of a pipelined processor?
A: The slowest pipeline stage and stalls from hazards.
Q: What is pipeline speedup?
A: The ratio of unpipelined to pipelined instruction execution time — ideally equal to the number of pipeline stages.
Q: What causes pipeline stalls?
A: Dependencies or hazards that prevent the next instruction from progressing.
Q: What are the three types of pipeline hazards?
A: 1) Structural hazards, 2) Data hazards, 3) Control hazards.
Q: What is a structural hazard?
A: A conflict in hardware resources preventing simultaneous instruction execution.
Q: What is a data hazard?
A: Occurs when instructions depend on results not yet available from previous instructions.
Q: What is pipeline forwarding?
A: A technique where results are passed directly to dependent instructions without waiting for them to be written back.
Q: What is a control hazard?
A: A delay caused by branch instructions that alter the program counter (PC).
Q: What is branch delay?
A: The time lost waiting to determine if a branch is taken.
Q: How can control hazards be reduced?
A: Using branch prediction and speculative execution.
