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AS Computer Science > Components of a Computer > Flashcards

Components of a Computer Flashcards

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1
Q

Computer (definition)

A

Electronic device that takes input, processes information using program and delivers output

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2
Q

3 basic steps of the FDE cycle (definitions)

A

Fetch - bring next instruction to be decoded from RAM to CPU

Decode - inspect instruction to work out components and functions needed

Execute - carry out and complete instructions

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3
Q

What happens in the Fetch stage of the FDE cycle? (5)

A

PC address copied to MAR
MAR requests data from RAM using address bus
MDR receives data from MAR address
PC increments
MDR copied to CIR

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4
Q

What happens in the Decode stage of the FDE cycle? (3)

A

Instruction split into opcode and operand to determine instruction type and hardware needed
Copy of data loaded to CPU is given to cache for easy re-access
Addresses written to MAR in preparation for more reading/writing in Execute stage

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5
Q

What can happen in the Execute stage of the FDE cycle? (3)

A

The opcode is carried out on the operand, which could mean:
A new address is given to the PC
Data is returned through the MDR to RAM
More data fetched for accumulator

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6
Q

Describe the CPU (purpose and parts)

A

The part of the computer dedicated to processing data and organising execution of instructions. Contains ALU, CU, cache and registers.

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7
Q

What does the ALU do? (3)

A

Makes logical decisions

Performs arithmetic calculations

Acts as gateway between primary memory and secondary storage

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8
Q

Examples of ALU functions (2)

A

ADD/SUBTRACT
AND/OR/NOT

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9
Q

What does the CU do? (2)

A

Directs data flow between processor and other components

Decodes instructions into sequential steps and manages execution + storage of results

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10
Q

What is cache?

A

High-speed RAM inside CPU used to store small amounts of data likely to be reused

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11
Q

Differences between L1 cache and L2 cache? (3)

A

L1 has faster transfer rates and more frequently used data, but is smaller and more expensive
L2 has slower transfer rates (still faster than RAM) and less frequently used data, but has larger capacity

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12
Q

What are registers?

A

Small, high-speed, on-board memory inside CPU, with designated purposes

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13
Q

What does the PC do?

A

Holds address of next instruction to be executed, either by incrementing or jumping to an address provided by the CIR

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14
Q

What does the CIR do?

A

Holds current instruction to be executed, divided into operand and opcode

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15
Q

What is the operand?

A

Data to be manipulated/operated on

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16
Q

What is the opcode?

A

An instruction to perform on the operand

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17
Q

What does the MAR do?

A

holds address of current instruction to be fetched/written to

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18
Q

What does the MDR/MBR do?

A

temporarily holds fetched data/data to be written

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19
Q

What does the ACC do?

A

holds data being processed by ALU and results of processing

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20
Q

What is a bus? (include capacity)

A

Set of parallel wires connecting components of a computer; usually 8-64 lines

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21
Q

Describe the system bus (purpose and parts)

A

Made up of address + data + control buses. A shared transmission medium between CPU, memory and I/O controllers

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22
Q

Describe the address bus (parts and purpose)

A

Transmits addresses of operands (“words”) from other components to RAM

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23
Q

What is a “word” (when discussing data - include estimated size)

A

Fixed size group of bits (usually 16-64 depending on the processor) treated as one unit of information and stored at one address

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24
Q

Describe the data bus (parts and purpose)

A

Bidirectional bus (8-64 lines) for transmitting data and instructions between components that request to use it.

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25
Q

How are processed results written to memory?

A

The MAR contains the address to write to and the MDR contains the data to write. The address is sent separately through the address bus and the data through the data bus.

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26
Q

Describe the control bus (parts and purpose)

A

Bidirectional bus which transmits command, timing and specific status information between components to ensure data/address buses are never used conflictingly

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27
Q

Control lines for buses (2)

A

Bus request = device requests use of data bus
Bus grant = CPU grants access to data bus

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28
Q

Control lines for memory (2)

A

Memory read = data from an address provided is to be sent through data bus to MDR
Memory write = data sent from MDR is to be written to address provided

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29
Q

Control lines for the CPU (2)

A

Clock = sent from CU to synchronise all operations
Interrupt request = device requests access to CPU

30
Q

How does number of cores affect CPU performance?

A

Each core runs its own FDE cycle so can execute almost twice as many instructions in the same amount of time

31
Q

Why would doubling CPU cores not double processing speed? (2)

A

Some processing power is devoted to coordinating cores

Programs that aren’t designed with parallel processing will still only work with one core so performance on that program would not change

32
Q

How does size of registers affect CPU performance?

A

Store data/instructions that the CPU is working on, hence more can be worked on at once if multiple processors are working on the same contents.

33
Q

How does size of RAM affect CPU performance?

A

Fetching from RAM is faster than fetching from virtual memory, so large RAM will improve performance when a lot of program is in RAM at once

34
Q

How does clock speed affect CPU performance?

A

The clock coordinates CPU activities with a crystal transistor. Increasing the clock speed (“overclocking”) will run more FDE cycles per second, but may damage the CPU.

35
Q

How does data bus size affect CPU performance?

A

A wider data bus can transmit larger words at once between components, reducing amount of fetches to send an entire program

36
Q

How does cache size improve CPU performance?

A

More data in cache = faster access times on the average instruction, reducing overall FDE times

37
Q

How could a faster CPU lose in benchmark tests to a slower CPU?

A

Slower CPU has larger cache/RAM

38
Q

What is important when increasing RAM size?

A

address bus size must be able to represent binary addresses of every location (one line = 1 bit)

39
Q

Assembly language (definition)

A

Low-level programming language which is very similar to the machine code

40
Q

Mnemonic (definition)

A

Simple name used to define a computing function

41
Q

Describe RAM

A

Volatile memory used to store the instructions/data for all programs currently running that could be needed by the CPU (e.g. apps, OS). Constantly being written to/read from.

42
Q

Describe ROM

A

Non-volatile flash memory store of basic programs such as BIOS

43
Q

What does BIOS do? (3)

A

Detects hardware, self-checks and copies the loader into RAM to load the OS

44
Q

What is RISC?

A

Reduced instruction set computer = uses a small, simplified instruction set. Aims for efficiency and speed through simplicity.

45
Q

What is CISC?

A

Complex instruction set computer = has extensive instruction set than can perform multiple operations with one instruction. Prioritises convenience and code density over execution speed

46
Q

Advantages of RISC (4)

A

Better instruction throughput as instructions are simple
Deeper and more efficient pipelining
More power efficient
Best for simple, repetitive tasks

47
Q

Characteristics of RISC (3)

A

Reduced instruction set

Large number of general purpose registers used directly

Load/store architecture (data must be loaded before it can be acted on)

48
Q

Advantages/disadvantages of CISC

A

Larger instruction latencies due to limited pipelining abilities
Longer decoding time as instructions are complex (e.g. multiple operands)
More efficient/easier to code when doing complex tasks as instructions can be represented with less code
Higher power consumption

49
Q

Characteristics of CISC

A

Extensive and complex instruction set
Memory is used more for operands than general purpose registers
Can do memory-to-memory operations with more complex addressing modes

50
Q

What is throughput?

A

How fast data can undergo a process

51
Q

What is pipelining?

A

Efficiency by organising components to maximise use (acting like a production line)

52
Q

Stored program concept (definition)

A

Instruction and data stored in the same memory which can be fetched from sequentially by CPU

53
Q

Characteristics of stored program concept (2)

A

Program instructions and data are stored in memory, usually with binary code

CPU fetches instructions one by one and executes them sequentially, using the PC to find the next instruction

54
Q

How does Von Neumann architecture use the stored program concept? Why is it good?

A

Von Neumann architecture treats instructions like data, allowing program to be written for new tasks and loaded into memory to be executed. This enabled the creation of general purpose computers that could be reprogrammed without rewiring.

55
Q

What is Von Neumann architecture?

A

Theoretical framework for a general purpose computer which can be reprogrammed without being rewired

56
Q

Characteristics of Von Neumann architecture (3)

A

Unified memory for data and instructions, with addresses to identify each segment

CPU executes instructions, using CU and ALU

Instruction set written in binary and can be executed sequentially by CPU using PC to load

57
Q

What is Harvard architecture

A

Theoretical framework for a computer with a specific purpose that DOES NOT USE stored program concept

57
Q

Characteristics of Harvard architecture (3)

A

Memory for data and instructions are separate “banks” with their own buses and storage units.

Data memory bank is used exclusively for retrieving and storing data and variables. Program memory/instruction cache is used exclusively for fetching and storing program instructions

Separate, specialised buses for instruction and data allow for efficient and independent transfers

58
Q

Potential advantages/disadvantages of Harvard architecture over VN architecture (3)

A

Parallel access = CPU can fetch an instruction from the instruction memory while simultaneously reading/writing data in data memory

Improved fetching and data access times in situations where frequent and concurrent access to data and instructions is needed

Can be more complex than VN architecture due to separate bus systems

59
Q

Where is Harvard architecture used?

A

Embedded systems and specialised processors where high-performance data processing is important e.g. microcontrollers and digital signal processor

60
Q

Multi-core CPU (definition)

A

Two or more independent processor cores on a single chip

61
Q

Advantages of a multi-core processor (4)

A

Better performance when using software designed for parallelism e.g. video games

More energy efficient than increasing clock speed on a single CPU

Improved responsiveness as background tasks can be delegated to other cores, with one core solely focused on user interaction

Number of cores can be scaled to meet performance/efficiency requirements, making design flexible

62
Q

Parallel processing (definition)

A

Breaking down a large task into subtasks to be delegated to multiple cores in a CPU

63
Q

How does parallel processing work?

A

Task decomposition is used to divide a complex task into subtasks which can be executed independently and concurrently

64
Q

Where is parallel processing used? By what components? (4 each)

A

Parallel processing can be done by a multicore CPU, multiple individual CPUs, GPUs, or specialized hardware accelerators.

Its used in scientific computing, data analytics, computer graphics and high-performance computing

65
Q

What are the two types of parallelism?

A

Data parallelism - same operation applied to multiple data elements simultaneously
(Used in image processing or numerical simulations)

Task parallelism - executing multiple subtasks concurrently

66
Q

Advantages of parallel processing (3)

A

Faster execution when a task can be divided into subtasks

Scalable by adding more processing units

More efficient use of available hardware resources, improving performance

67
Q

Potential disadvantages of parallel processing (2)

A

Amdahl’s law = the overall increased speed is limited by sequential portions of the task (things that must be done in an order)

Synchronisation of tasks and management of shared resources is complex

68
Q

Describe SIMD (meaning, purpose)

A

Single instruction, multiple data = parallel process where one opcode is done on multiple operand

69
Q

What is SIMD architecture used for?

A

Used by GPUs and vector processors for image processing, video encoding and simulations on large datasets as it is efficient for tasks requiring the same operation

70
Q

Describe MIMD (meaning, purpose)

A

Multiple instruction, multiple data = independent processing units each with their own PC and instruction stream

71
Q

Where is MIMD architecture used?

A

Used in modern multicore CPUs and distributed computing systems for general purpose, scientific simulations, parallel processing of diverse workloads

AS Computer Science (7 decks)

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