comp arch

Question 1

advantage and disadvantage of more data type

Answer 1

benefit is code is smaller and faster or more optimised.

disadvantage is this is more work for the microarchitect

Question 2

advantages and disadvantages of complex instructions and data types

Answer 2

advantage: denser encoding -> smaller code size -> better memory footprint of instructions, saves off chip bandwidth, fewer cache misses
simpler compiler

disadvantages compiler has less opportunity to optimize. larger chunks of work. more complex hardware

Question 3

what is the 5 stage pipeline

Answer 3

IF ID EX MEM WB

Question 4

what isa does apple ues?

Answer 4

ARM except for on the watch OS

Question 5

data path and control path in multi cycle and single cycle machines?

Answer 5

single cycle:
control signal are generated in the same clock cycle as the one during which the data signals are operated on.
everything related to an instruction happens in one clock cycle

multi cycle:
control cycles needed in the next cycle can be generated in the current cycle
latency of control processing can be overlapped with latency of datapath operation (more parallelism)

Question 6

advantages and disadvantages of a multi clock cycle design

Answer 6

advanatges:
*higher clock freq as we are only limited by time of longest step in a stage
*simpler instructions take only a few clock cycles
* we can reuse expensive hardware across multiple cycles

disadv:
* hardware overhead for storing intermediate results in registers
*sequential logic overhead paid many times for each instruction

Question 7

what is the motivation to go from single cycle to multi cycle?

Answer 7

1. In a single-cycle processor, each instruction must complete within one cycle, which typically requires making the cycle long enough to accommodate the slowest instruction.
2. resources can be shared. like ALU for address addition and ALU for add operation
3. complex instructions possible as they don’t limit simple instructions
4. Cycle Time Reduction: Multi-cycle processors break down the execution of an instruction into several shorter steps, each completing in one cycle.

Question 8

what are causes of pipeline stalls?

Answer 8

data dependence
control dependence

resource dependence/contention

Question 9

how to handle resource contention?

Answer 9

duplicate the resources.

detect the pipeline stages that want resources and give to the one ahead so that the pipeline can keep moving

Question 10

What optim can you do since reg operations are fast

Answer 10

since register operations are super fast you can do operation in front of the pipeline in the first half and do the operation behind in the second half

Question 11

what are the types of data dependence

Answer 11

1. flow dependence: a consumer instruction is reading a data a prior instruction has written to (ReadAfterWrite dependency)
   r3<-r1 or r2
   r5<- r3 or r4
   This is a true dependence as there is data flow
2. Anti dependence : Write after read dependence (WAR). not a true dependence
   r3<- r1 op r2
   r1 <- r4 op r5
3. output dependence: Write after Write (WAW dependence)
   r3<- r1 op r2
   — r5 <- r3 op r4
   r3 <- r6 op r7

Question 12

what is interlocking?

Answer 12

detection of dependence between instructions in a pipelined processor to guarantee correct execution

you can do interlocking in software or hardware

MIPS - microprocessor without interlocking pipeline stages.

Question 13

what is scoreboarding?

Answer 13

Scoreboarding:
Each register in register file has a valid bit associated with it.
An instruction that is writing to the register resets the valid bit
an instruction in the decode stage checks if its source and destination registers are valid

Question 14

what are approaches to dependence detection?

Answer 14

scoreboarding and conbinational dependence check logic

Question 15

what is combinational dependence check logic?

Answer 15

you compare at decode stage if the register you’re going to read or write is being written to by any of the stages ahead using comparator and then stall if there is a dependence

Question 16

what is data forwarding?

Answer 16

if a value an instruction needs is not ready because it hasn’t been written by an incomplete instruction in the pipeline but it has been computed then it can be forwarded directly without waiting for writing into registers

Question 17

Reasons for pipeline stalls

Answer 17

Resource contention

Data/ Control dependence

Long latency operations

Question 18

when might it be difficult to do data forwarding?

Answer 18

if you have to forward data from MEM stage which is often the bottleneck this might increase cycle time and so you might not want to do that

Question 19

what is control dependence?

Answer 19

when you have branch or conditional jump and stuff you don’t know what the pc is for next instruction so you would have to stall

Question 20

how do you resolve control dependence?

Answer 20

branch prediction

Question 21

variable length execution due to multiplication with what inputs? what does this means about hardware vs software optimizations

Answer 21

if you’re multiplying by 0 you could be done super fast and only hardware knows this during runtime and can process this to benefit

Question 22

what is fine grained multithreading

Answer 22

you overlap stages from multiple threads to get faster processing as you can now get more flexibiility with stalls

Question 23

how does multi cycle execution stages affect pipelining

Answer 23

it results in wb for all instructions after the multistage execute to stall till multistage execute is complete

Question 24

how do you solve multicycle execute causing issues in pipelining?

Answer 24

you use

Question 25

if you have a multi cycle execute which is independent to instructions after it can you complete those instructions before multicycle execute finishes?

Answer 25

no as this violates von nuemann arch and also is a problem if you have an exception in the multi cycle instruction like say you have a divide by 0 error and you have to stop program, then the system expects the program to have end there and future instructions to not have executed.

hence you can’t do this. maybe the machine wants to do a try catch or maybe it will end program and expects a different state. S0 cannot violate von nuemann arch

Question 26

what are interrupts?

Answer 26

something which results in the program to stop or change. Like exceptions this becomes a reason why you can’t violate von nuemann and need reorder buffers

Question 27

what are reorder buffers?

Answer 27

after an instruction completes you write into a reorder buffer and you write to register (WB) only after an instruction before it has finished.

it is implemented as a circular queue

Question 28

how are WAR and WAW dependencies handled?

Answer 28

by renaming to reorder buffer register names

Question 29

why out of order execution and how?

Answer 29

so that independent instructions aren’t bothered by stalled prior instructions.

how is by creating a dataflow graph so that you execute when inputs are ready

Question 30

what changes in modern pipeline with out of order execution

Answer 30

reservation stations after IF and ID,

reorder buffer after EX,

if and id in order, ex out of order and wb in order after that

Question 31

what is superscalar execution?

Answer 31

you do IF, ID, EX, MEM, WB for N instructions to same cycle

Question 32

tag bits, index bits, bytes in block

Answer 32

8 bit address -> 2 3 3 split

3 bytes in block means 1 block has 8 bytes

3 index bits mean 8 blocks can be stored in cache

2 tag bits are matched with tag position in cache to check for hit or miss

Question 33

translation lookaside buffer

Answer 33

used to map virtual memory address to main memory address