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Year 1 Semester 1 > Comp 1313 Systems 1 > Flashcards

Comp 1313 Systems 1 Flashcards

1
Q

What is a combination circuit?

A

An Interconnected set of gates whose output is a function of the input at a time.

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2
Q

What is a tri-state?

A

A gate with a extra input that disables the gate, used to prevent short-circuits.

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3
Q

How would I make a two variable Karnaugh Map?

A
  1. Create a table using your two variables, e.g A on top row and B on the first column
  2. Fill the next row/column with the possible values of the variables.
  3. Use the expression to calculate what result in 1, and place these in the table.
  4. Draw rectangles of size 2^n boxes around the ones. They cannot be diagonal and must be as big as possible.
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4
Q

How do you decipher a Karnaugh Map?

A
  1. Take each box
  2. If the digit in the heading stays the same keep it, otherwise discard the box
  3. The boxes left represent the expression
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5
Q

Why can’t machine code be run on different machines?

A

As different CPU’s have different instruction sets.

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6
Q

The clock is an electronic pulse. So when does the CPU perform an action?

A

On a clock edge

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7
Q

What is RISC?

A

Reduced Instruction Set Computer

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8
Q

What is CISC?

A

Complex Instruction Set Computer

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9
Q

How can runtime be calculated?

A

Runtime = instruction-time x cycles per instruction x Number of instructions

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10
Q

What is the difference between RISC and CISC?

A

RISC often has one instruction per cycles, while CISC instruction are more complex and therefore can take multiple cycles.

CISC will look much nicer than RISC code.

CISC aims to reduce Ninstr while RISC reduces the cycles per instruction

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11
Q

What is a register?

A

A group of flip-flops that can store multiple bits. Used as temporary storage on the processor.

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12
Q

What is a shift register?

A

They shift a bit every single clock cycle along the register. This is used to convert between serial and parallel data.

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13
Q

How many registers (general purpose) are needed?

A

16ish

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14
Q

Where are registers on the memory hierarchy?

A

Top

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15
Q

What is a general purpose register?

A

They store the CPU’s current required data.

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16
Q

How big is a register (general)?

A

Word length or more depending on if it has a specific purpose (e.g storing floating points)

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17
Q

What are the 6 types of registers?

A

Address only
General purpose
Condition Code
Status/flags
Control
Special

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18
Q

What can be stored in an address only register?

A

Just a memory address

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19
Q

What is the purpose of a Condition Code register?

A

Set of individual bits that indicate if an error has occurred.

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20
Q

Can a condition code register be written to be a program?

A

Not usually, but they can be read from

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21
Q

What is a Status/FLAGS register?

A

A register contain condition code or the sign of a result, an overflow indicator.

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22
Q

What are control registers?

A

A set of registers that are hidden by the CPU. This includes the MBR, MAR and others.
The PC is the only control register readable by assembly

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23
Q

What is a special register?

A

An additional register used for a specific function, like storing vectors. Usually implemented on CPU’s that have a specific purpose.

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24
Q

What is a pipeline?

A

Overlapping instructions with the aim to complete one instructions per cycle rather than one stage per cycle (if that).
Similar to an assembly line.

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25
Q

What can ruin pipelining?

A

Branching

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26
Q

How can we deal with branches?

A

Multiple streams
Prefetch Branch Target
Loop buffer
Branch Prediction

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27
Q

What is Prefetching the Branch target

A

Prefetch the branch target and a few instructions after before the actual branch

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28
Q

What is loop buffering?

A

Very fast memory that store the last n instructions, maintained in the fetch stage of the pipeline.
Check the buffer before fetching, and then load the buffer instead.
Good for small loops

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29
Q

What is Branch predicition?

A

Predict where you’re going to branch.
This involves predict that you either will always branch here or will never branch here.
If so we either prefetch the next instruction or the branch instructions.

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30
Q

How can we improve branch prediction?

A

Predicting by Opcode. As some are more likely to jump than others (75% success rate)

Taken/Not taken switch, use previous execution history to detirmine if it’s going to jump.

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31
Q

What is overloading?

A

Operators have different meanings in different algebras.

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32
Q

How many bits can be stored in a register of length n?

A

2^n-1

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33
Q

What are some benefits of biased offset?

A

Eliminates negative values
Simplifies comparison operations
Symmetrical range about zero
Facilitates floating point
Simpler conversion between systems

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34
Q

What does two’s complement avoid?

A

Avoids the double representation of zero

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35
Q

How to convert to two’s complement?

A

Flip every bit and then add one

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36
Q

How to convert to biased-n?

A

Add the bias to the original number and then convert to an unsigned binary number

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37
Q

What is biased-n?

A

Shifting by a bias so that 0000… would be -128 and 1111… would be 128

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38
Q

What is superscalar?

A

Doing simple commands at the same time using multiple arithmetic units.
Basically not vector or array logic

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39
Q

What is true data dependency?

A

When one instruction is dependant on another instruction happening previously and thus cannot execute together.

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40
Q

What is procedural dependency?

A

Can’t execute instructions after a branch with instructions before, otherwise we waste processor time.

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41
Q

What is resource conflict?

A

Two or more instructions request the same resource at the same time.

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42
Q

How can resource conflict be resolved?

A

By duplicating the resource

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43
Q

What is instruction level parallelism?

A

Instructions in a sequence are all independent of each other, so their execution can be overlapped.
Governed by data and procedural dependency.

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44
Q

What is machine parallelism?

A

Ability to take advantage of instruction parallelism.

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45
Q

What is an instruction issue?

A

Where the order of instructions, fetched, executed, memory and registers changed.

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46
Q

What is an In-order issue?

A

Issuing instructions in the order the occur
This is inefficient
Instructions could stall if required

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47
Q

What is an out-of-order issue?

A

Decouple, decode pipeline from the execution pipeline.
Continue to fetch and decode until the pipeline is full, when a unit becomes available then we use it.

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48
Q

What are the result of out-of-order issue?

A

We need additional logic to ensure that our code isn’t destroyed by being executed out of order.

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49
Q

What is antidependancy?

A

One instruction cannot happen before another, as the first instruction modifies the other instruction’s operands.

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50
Q

What is register renaming?

A

Avoid antidependancy by dynamically allocating registers as they are needed to have copies of the original values before have the code reference that version of the registers. These are stored in register specifically for this.
Avoiding pipeline stalls.

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51
Q

What is machine parallelism?

A

Duplication of resources with out-of-order issues.
Need instruction window length large enough to “see” instructions incoming.

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52
Q

What is speculative execution?

A

If there is a unit free we can do instruction that may be needed. And dispose of their results if they are not.
Out of order execution can provide this, but, leads to the meltdown vulnerability.

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53
Q

What are the two main families of OS?

A

Microsoft Windows and UNIX-like

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54
Q

What do OS provide programmers?

A

An easy and convenient interface with the system.

It is essentially a mediator between programs and hardware.

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55
Q

Why does the OS conceal complexity?

A

To protect users and programmers from having to work with horrendous complexity. (IP, Compilers, Drivers)

To protect users and programmers from the details of the hardware through an interface.

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56
Q

What does the kernel provide?

A

Memory management
Task management
File management
Device management

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57
Q

What is kernel memory management?

A

Allocation of memory and management of virtual memory
Also restricts access helping with programming errors and malware.

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58
Q

What is kernel task management?

A

Launching processes
Maintaining the process table in memory
Performing time slicing and context switching
Handling interrupts

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59
Q

What is kernel file management?

A

Respond to program request to open files
Set and check permissions
Handle buffering

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60
Q

What is kernel device management?

A

Use drivers to respond to request to use devices.

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61
Q

What essential features are required for an OS?

A

Memory protection
Timer
Privileged instructions
Interrupts

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62
Q

What is scheduling?

A

Making effective use of the processor because the processor is much faster than memory or I/O devices, so scheduling is required so that other task can be completed while one waits.

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63
Q

What is context-switching?

A

The state of a running process is saved, and another process given processor resources

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64
Q

What does PCB stand for?

A

Process Control Block

Comes with an:
Identifier
State
Volatile environment
Priority
I/O status
Accounting information.

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65
Q

What are the types of scheduling?

A

Long-term
Medium-term
Short-term
I/O

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66
Q

What is swapping?

A

When space becomes available processes are loaded from disk and when they are stalled or finished they are removed.

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67
Q

What is partitioning?

A

How do we distribute a set of processes (of unknown and varying sizes) onto fixed memory.

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68
Q

What are fixed partitions?

A

Partitions of memory of a fixed size

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69
Q

What are variable partitions?

A

Partitions allocated as required, may lead to fragmentation

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70
Q

What are the three types of address involved in partitioning?

A

Logical Address, location relative to beginning of the program

Physical address, the actual location in memory

Base address, current starting location of the process

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71
Q

What is paging?

A

We divide memory into lots of small, equal chunks (frames)
Divide processes into chunks (pages) of the same size as these frames
Then we can map pages to frames efficiently (in terms of memory)

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72
Q

How do we link a logical and physical address?

A

Through the page table

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73
Q

Why do we need page tables?

A

Page tables show exactly what pages belong to what process, by translating base address to physical address.

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74
Q

What is demand paging?

A

Each page of a process is swapped in only when it is needed.

This makes it possible for a program to be larger than memory as only pages required are loaded, a page fault is triggered to inform the OS that a new page is required.

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75
Q

What are the advantages and disadvantages of demand paging?

A

Advantages:
More processes can be maintained
Time is saved

Disadvantages:
This uses swapping, so one page in and one out.
Thrashing can occur - Where the processor spends most of it’s time swapping pages.

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76
Q

T/F The process table can be paged out

A

True

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77
Q

What is the TLB?

A

Translation lookaside buffer
Every logical access requires two physical access, page table entry and the actual access
Most systems have cache reserved for TLB

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78
Q

What is segmentation?

A

Allowing the programmer to view memory as a series of address spaces or segments.

Good for handling growing data structures
Recompilation independently without requiring an entire set of programs to be recompiled
Sharing among processes
Protection

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79
Q

What is simultaneous multithreading?

A

One core can look like two with extra instructions but sharing execution units allowing separate threads to run.

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80
Q

What is power management?

A

Using a separate microcontroller to monitor power
Can shut-off cores and boost cores when required.

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81
Q

What is a turbo boost?

A

We can turbo-boost a core for short burst or if we are only running a single core.
Used widely.
1 or 2 cores active at 5Ghz
or 3-4 active at 4.8
or 5-8 active at 4.7

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82
Q

In modern systems, is RAM connect to the CPU or the Chipset on the motherboard

A

Directly to the CPU.

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83
Q

What is NUMA?

A

Non-Uniform Memory Access
Multiprocessor systems with separate blocks of RAM to reduce bottlenecks and is good with large numbers of cores

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84
Q

What is an NPU?

A

Neural Processing Unit
specialist unit in a CPU for neural net calculations

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85
Q

What is the hybrid architecture?

A

Using a mix of performance and efficency cores.
As processes using less resources can run on E cores
E cores are much smaller than P cores

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86
Q

What is a network?

A

Multiple computer that are connected together and can share information/resources

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87
Q

What is a WAN, LAN, MAN and PAN?

A

Wide Area Network
Local Area Network
Metropolitan Area Network
Personal Area Network

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88
Q

What are the two network models? And why are they layered?

A

OSI
TCP/IP

Abstraction, so we don’t need to know about the hardware.

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89
Q

What are the layer of TCP/IP?

A

Application
Transport
Internet
Network Access (Link)

90
Q

What is the End-to-End concept?

A

The network is responsible for best-effort connections
End-hosts are responsible for reliability and security

91
Q

What is the Network Access Layer?

A

Deals with local link
With a unique MAC address

Ethernet

92
Q

What is the internet layer?

A

Handles next-hop routing provides unique addressing
Passes to the correct devices, transport layer.

93
Q

What is IPv4?

A

32 bit IP address
Variable length header with a minimum of 20-bytes
We have run out of IPv4 addresses

94
Q

What is NAT and NAPT?

A

Sharing one IPv4 address between multiple computers
Breaks the end-end principle
Doesn’t solve the exhaustion problem

95
Q

What is IPv6?

A

128-bit address with a 40-bytes header
Written in hex

96
Q

What is a subnet?

A

A logical subdivision of a network

97
Q

What is routing?

A

When there is a change in IP spaces, at the internet layer, packets are changed to have new IP addresses and converted between networks.

98
Q

What is the Transport layer?

A

Provides host-to-host communication using TCP and UDP

99
Q

What is TCP?

A

Acknowledgements
Guanteed arrival in correct order
20-bytes header

100
Q

What is UDP?

A

No acknowledgements required
No guarrentee on order
8-bytes header

101
Q

What is flow control?

A

Preventing a fast sender overwhelming a slow responder

102
Q

What is congestion control?

A

Reduces send rate to cope with network congestion.

103
Q

How does TCP implement flow control?

A

Sliding window protocol
The sender should only send if the receiver indicates that it has suitable buffer space

104
Q

How does TCP implement congestion control?

A

Sender sends a small packet and increases size until a packet is lost.
Sender restarts the cycle of sending with a lower threshold

105
Q

What is the application layer?

A

Software that uses the networks, generally using pre-made libraries themselves.

106
Q

What is ICMP?

A

A protocol used for diagnostic and control purposes or generated in response to error in IP

107
Q

What addressing does the Transport layer use?

A

Port number

108
Q

What is ADR / NDP?

A

Address Resolution Protocol
Neighbour Discovery Protocol

Operates at the link layer
Translates IP addresses to MAC addresses

109
Q

What is DNS?

A

Domain Name Service provides a way to map symbolic domain names to an IP address
Reliable and resilient distributed service
At the application layer

110
Q

What devices can be used to expand a network?

A

Hubs
A multi-port repeater
All packets sent to all connected devices

Switches
connect multiple devices on one network segment
Switches are at the Link layer
They forward only to the specific required port

111
Q

Why are we monitored?

A

So network owners need to know what is happening
Government want to know what people are doing

112
Q

How can we stay anonymous?

A

VPNS create a logs anyway and their exit points can be monitored

ToR- The Onion Router
Routing traffic through a random series of hops, all encrypted.

113
Q

What is an instruction set?

A

List of all commands that a processor can execute
It is per processor

114
Q

What are the elements of an instruction?

A

Operation Code
Source operand reference
Result reference
Next instruction reference (usually implicit)

115
Q

What are the instruction types?

A

Data processing
Data movement
Program flow

116
Q

Why do we have shifting a rotating instructions?

A

For shifting:
Bit masks
Unpacking data
Fast integer arithmetic

For rotating:
cryptography

117
Q

How can I/O be accessed by instruction set instructions?

A

May be specific instructions
May be done with data movement instructions
May be done by a separate controller

118
Q

How many addresses should we have per instruction?

A

More addresses:
More complex instructions
More egisters
Reg-Reg operations are quiker
Fewer instruction per program

Fewer addresses:
Less complex instructions
More instructions per program
Faster fetch/execution of instructions

Comprimise!

119
Q

What is RISC and CISC?

A

Complex Instruction Set Computing
Multiple cycles per instruction

Reduced Instructions Set Computing
One cycle per instruction (usually)

120
Q

What is endianness?

A

There is no consistency in ordering bytes

121
Q

What is big endian?

A

Most significant byte in the lowest numerical address

Memory dumps are left to right
Stores strings and integers in the same order
But has to perform an extra operation to convert 32 bit to 16 bit addresses

122
Q

What is little endian?

A

Least significant byte in the lowest address

123
Q

What are the four types of Instruction Set Architecture?

A

Accumulator
Stack
Register-memory
Register-Register

124
Q

What is the accumulator ISA?

A

The accumulator is the input and output store
A can be loaded
B can then be added
The result can be stored

125
Q

What is the stack ISA?

A

Operands are pushed onto a stack and then an instruction POPs them off, performs the operations and pushes them back.This requires an extra pointer, and memory transfer requires extra operations.

126
Q

What is register-register ISA?

A

Operand LOADed from memory to registers
Instructions use operands stored in registers
Memory transfer requires extra operations.

127
Q

What are the pros/cons of the types of ISA?

A

Accumulator
Short instructions

High memory traffic
Single temporary storage location

Stack
Simple
Short instructions

Stack cannot be randomly accessed
Bottleneck in stack

Register
Easy code
Compiler optimisations
Fast access to temporary values

Operand must be names
Longer instructions

128
Q

What does the status register do?

A

Shows information about an instruction, if problems occured, the result of previous instructions, etc.

129
Q

What is the link register?

A

The return address of a branch is placed in the link register so that a subroutine can return back

130
Q

Why do return addresses use a stack?

A

This allows the occurance of multiple subroutines.

131
Q

What is the memory cycle time?

A

Time required for memory to recover before next access

132
Q

What is the storage hierarchy?

A

Register
L1 Cache
L2 Cache
Main Memory
Disk cache
Disk (SSD)
HDD
Optical
Tape

133
Q

What is DRAM?

A

Dynamic RAM
Requires refreshing or charges will leak
Simple and small, less expensive
25GB/s

DDR5
Two 32 bit channells
38GiB/s up 96GB

134
Q

What is SRAM?

A

Static RAM
Bits stored as on/off gates using 4-6 transistors
No charge leak so no refreshing
More expensive and more complex

135
Q

What is ROM?

A

Read-only memory
BIOS anbd basic system programs

136
Q

Why is error correction required?

A

DRAM looses data, 25K failures per Mbit per billion hours

137
Q

What are Hard and soft failures?

A

Hard
Permanent defect

Soft
Random, non-destructive
No permanent damage

Detected and maybe fixed by Error Correcting Code

138
Q

What is cache?

A

Small block of fast SRAM on the CPU where memory requests are sent (NOT DRAM)

139
Q

Why is latency important for memory?

A

As DRAM takes at least 5 clock cycles to provide data

140
Q

How does cache operate?

A

CPU reads a memory location
Address goes to cache
If present cache will provide (hit)
Otherwise, block read required from RAM to cache (miss)
Then this is delivered

141
Q

Why is cache split into instruction and data?

A

As they have different access patterns

142
Q

Why is a level 2 cache used?

A

As bigger caches have longer latency so they need to be split

143
Q

How many levels of cache are used in total?

A

3

144
Q

What is the memory connection?

A

N words of equal length with unique address

145
Q

What is the CPU connection?

A

Reads instructions and data
Sends controls signals to othe units
Defines a chip plug

146
Q

What are the bus structures?

A

Control/Address/Data
PCIe
Serial ATA
Universal Serial Bus

147
Q

What is a shared bus?

A

A common communication pathway
Signals might be separate, multiplexed, serialised
This convers the conventual parallel bus.

148
Q

How wide is a general parallel bus?

A

64 bit

149
Q

What does address bus width detirmine?

A

Maximum memory capacity

150
Q

What does the control bus contain?

A

Control and timing information
Controls access to other buses

151
Q

How can a module get to use a shared bus?

A
  1. Obtain the use of the bus
  2. Transfer data
  3. Synchronise and acknowledge
152
Q

What is PCIe?

A

Peripheral Component Interconnection Express
Serial bus with multi- GiBytes/s lanes
v5 - 4 GiByte/s

Uses 16 lanes for GPU cards

153
Q

How does PCIe work?

A

Packets are sent over serial links
ACK/NACKS protocol used for data safety
Using multiple lanes to gain bandwidth
It is similar to a network with layers and addressing

154
Q

What is used for hard-disk connectivity?

A

SATA - 500MB/S
SAS - 1.2GB/S
Fibre channel - 100 MB/S - 25 GB/S (long distance)
SCSI 10 - 640 MB/S
iSCSI
SAS

155
Q

What is USB?

A

Universal Serial Bus
For low-high speed I/O devices
Allows for 127 devices

USB4 - 10-40 Gbit/s

156
Q

How does USB work?

A

Assumes a root hub connected to the main bus
Cables have 4 wire
2 data lines
0 is a transition in voltage and 1 is the absence of a transition
Every 1 msec, the hub broadcasts a frame

157
Q

What are the 4 types of USB frame?

A

Control
Isochronous
Bulk
Interrupt

158
Q

What is BIOS?

A

Basic input/output system
Firmware on the motherboard to start and test hardware and boot OS.
Stored in flash and looks for a bot-loader

159
Q

What is UEFI?

A

A replacement for BIOS to boot services and runtime services and can have graphics

160
Q

What does the chipset define?

A

The paths/buses between componants

161
Q

What are the average speeds for each item?

A

DDR5: 10GB/S
PCIe V3: 1GB/S
PCIe V4: 2GB/S
V5: 4GB/S
Nvme SSD: 5GB/S
Sata SSD: 500MB/S
2.5Gbe: 200MB/S
Wifi 6: 100MB/s
Ethernet: 100MB/S
DMI V4: 16GB/S
HDD: 100MB/s
CPU: ~50 Gflops

162
Q

What is a magnetic disk?

A

A metal disk coated in magnetic material
They store data on multiple platers with one head per side, all aligned. Data is striped per cylinder to reduce head movement. Data is organised into concentric rings with gaps between rings.

163
Q

How is the speed of a HDD determined?

A

By the seek time.
Access time = seek time + latency

164
Q

Why is throughput a problem? And how is it mitigated?

A

Disk throughput will often be slower than the connection speed of the wire, on disk-cache can be used to store whole tracks.

165
Q

What is MTBF?

A

Mean Time Between Failures
HDD: 114 yrs

166
Q

What is an SSD?

A

Solid State Drive
non-volatile NAND logic with fast access times.

Over millions of writes the flash blocks can fail. File systems are used to deal with SSD problems and erase unneeded blocks, but only by block.

167
Q

Why do SSDs have controllers?

A

To perform interface addressing, error detection and correction.
To change some bytes a block has to be read and modified.

168
Q

What is the speed and capacity of Blu-ray?

A

70MiB/s read
15-30GiB average
128 GiB maximum

169
Q

What is a jukebox?

A

A collection of disks or tapes (blu-ray) which can be interchanged to read/write. Usually used for backup.

170
Q

What is iSCSI and SAN?

A

Internet Small Computer System Interface
TCP/IP over normal Ethernet that backs up data

Storage Area Network
Block accessed with 16GBi/s fibre channel

171
Q

What is a microcontroller?

A

A self-contained computer on a single chip featuring a slower clock.

172
Q

What does having no MMU mean for a microcontroller?

A

They can’t run a real operating system

173
Q

How much power do microcontroller use while active?

A

< 10mA

174
Q

How can microcontrollers be programmed?

A

Bare-metal programming
Embedded OS
Real-time

175
Q

What is bare-metal programming?

A

Write C code, compile it and then flash it to the micro-controller.

176
Q

When is real-time microcontroller programming used?

A

Used when the timing is crucial and must be guaranteed.

177
Q

What is system-on-chip?

A

Integrating most of a computer onto a single chip. Includes radio, co-processor, interface drivers and more.

178
Q

What is the hypervisor?

A

Software placed between the OS and hardware, that tells the OS what is and isn’t hardware.

179
Q

What is virtualisation?

A

Using a hypervisor to emulate hardware, above the hardware.

180
Q

What is a VMM?

A

A Virtual Machine Monitor is a layer of software that emulates the hardware of a complete computer system.

181
Q

Why is binary translation needed?

A

The machine code of the above OS may not be for the instruction set of the hardware.

182
Q

What is Paravirtualisation?

A

Changing the guest OS so that it cooperates with the Virtual Machine.

183
Q

When does a VMM expose hypercalls?

A

Activate and deactivate the interrupts
Change page tables
Accessing virtualised peripherals

184
Q

What is Hardware assisted virtualisation?

A

Allows the VMM to run privileged code.
It is not translated.

185
Q

How does HAV begin?

A

New instruction that switches the CPU into non-root mode.
Processor state is loaded from the guest state of the VM scheduled to run.
The control transferred from VMM to the VM.

186
Q

How does HAV end?

A

Saves the process state in the guest state area of the running VM.
Loads the processor state from the host-state area.
Transfer control to the VMM.

187
Q

What is KVM?

A

Linux device driver for hardware virtualisation.

188
Q

What is QEMU?

A

Uses binary translation via Tiny code generator for efficient emulation.

189
Q

What is a lightweight container?

A

Use the kernel of the host system to run only the code needed instead of having a full OS.

190
Q

What are the typical use cases of a VMM?

A

Freezing an older OS/demo service
Trying new OS.
Working on system installation scripts.
Migrating between VMs
Disaster recovery

191
Q

What is Flynn’s Taxonomy?

A

Classification of computer architectures.
Four classification based on number of instruction and data streams
But vector processing is missing.

192
Q

What is SIMD processing?

A

Do they same thing to many data objects

Require special CPU hardware and supporting software.

193
Q

What can SSE be used for?

A

Image processing
Video processing
Array/vector processing
Text processing

194
Q

What does SSE stand for?

A

Streaming SIMD Extensions

195
Q

What is SSE?

A

128-bit registers that can be packed with various data types.

196
Q

What processing model does a GPU use?

A

SIMD

197
Q

What is SMP?

A

Symmetric Multiprocessors

A MIMD system where multiple CPUs share main memory and I/O
Hardware manages contention.

198
Q

Describe a typical SMP system

A

Each processor has its own L1 and L2 cache
Connected by a system bus
Main Memory, I/O, etc are also connected to the bus.

199
Q

What is Heterogenous Multi-processing?

A

Combining big performance cores with little efficiency cores.

200
Q

What is Simultaneous Multithreading?

A

Hardware multi-threading on superscalar CPUs.

Execute multiple instructions at the same time using redundant execution units in the processor.

201
Q

What is Task parallelism?

A

Split the code up, onto separate CPUs

202
Q

What is the embarrassingly parallel problem?

A

Very easy to split tasks into parallel subtasks

203
Q

What is Data parallelism?

A

Split the data to make independent parallel tasks

204
Q

What are GPUs used for?

A

Video compression
Video transcoding
Image compression
Modelling
AI
Number-crunching

205
Q

What is a CUDA core?

A

A core containing a floating point unit and maybe an integer unit

Could have a Special Function Unit for trigonometric operations

206
Q

Why are DRAM chips arranged around the GPU?

A

As the bandwidth needs to be huge.

207
Q

What is a tensor core?

A

A core for AI acceleration

For fused multiply-add operations

208
Q

Why do some GPUs not need outputs?

A

Cards designed for number-crunching, especially in data centres don’t have outputs

209
Q

What is Moore’s law?

A

The number of transistors within a system doubles every two years

210
Q

What is Amdahl’s law?

A

The speed of a system is limited by it’s bottlenecks, there is a fancy equation for this.

211
Q

What is SMT?

A

Simultaneous multithreading

212
Q

What are the four parallel classifications?

A

SISD: Single Instruction Single Data
SIMD: Single Instruction Multiple Data
MISD: Multiple Instruction Single Data
MIMD: Multiple Instruction Multiple Data

213
Q

How are 3D objects represented?

A

A collection of Vertices, Edges and Faces

214
Q

How many reserved IPs are there?

A

2
The router and broadcast

215
Q

What is the length of a MAC address?

A

48 bits

216
Q

In an IPv6 address, what does :: mean?

A

Where 0s are, but, have not been included

217
Q

How many CUDA cores are in a GPU?

A

~20,000

218
Q

What are the two binary formats of IEEE 754?

A

Single (32 bits) and double (64 bits)

219
Q

How many bits are in a IEEE 754 single mantissa?

A

23 bits

220
Q

How many digits of precision do you get with double IEEE 754?

A

15-17 digits

221
Q

What are the 6 steps for converting a number to binary IEEE 754 representation?

A

Convert your number to binary
Normalise the number
Determine the sign bit
Calculate the exponent
Calculate the mantissa
Combine all the parts together

222
Q

What is Pulse Width Modulation?

A

An on/off signal used by motors and LEDs.

Year 1 Semester 1 (4 decks)

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