Coding mistakes

Question 1

Define module with inputs/outputs

Answer 1

Stuck at :
module rr_3_2_switch;
output ask_for_it;
input req[3:0];
…..

<logic>
endmodule;



Answer :
module rr_3_2_switch
#(parameter M_CNT=3,S_CNT=2)
(
output logic ask_for_it;
input wire req[2:0]
.....);

<logic>
endmodule;
</logic></logic>

Question 2

SV scheduling queue

Answer 2

1) Preponed

2) Active
3) InActive
4) NBA
5) Observed

6) Re-Active
7) Re-inactive
8) Re-NBA

9) Postponed

Question 3

Preponed region

Answer 3

*) #1step sampling delay provides the ability to sample data immediately before entering the current time slot
*) Sampling in the Preponed region is equivalent to sampling in the previous Postponed region.

Question 4

How does below code work : (switching between #0 to active code)

a = 1;
#0 b = 1;
c = 2;

c=1;
b=2;

Question 5

NBA working (variable used in nba is updated by nba)

a => b& c;
b=1;
c = 1;
b=>2;

d = b& c;
b=2;
c = 3;

Question 6

Observed region

Answer 6

Evaluation of concurrent assertions

Question 7

Reactive region

Answer 7

*) blocking assignments in program blocks
*) Action blocks of concurrent assertions

Question 8

Re-inactive region

Answer 8

0 in reactive region code : i.e

*) #0 in program blocks
*) #0 Action blocks of concurrent assertions

Question 9

Re-NBA

Answer 9

=> in reactive region code : i.e
1.=> in program blocks
2.=> Action blocks of concurrent assertions

Question 10

Postponed

Answer 10

$monitor, $strobe

=== preponed on next clk

Question 11

$monitor vs $strobe vs $write vs $display

Answer 11

• $display : is the normal display, which executes its parameters wherever it is present in the code.
• $write : similar to $display except contents are displayed in the same line.
• $strobe : only once in a time instant, when all processes in that time instant have executed. (postponed)
• $monitor : executes only if any of its parameters change (in one time instant). (postponed)

module d11; 
bit a=0, b=0; 
initial
begin
a=0; 
b=1; 
$display(a,b); 
$strobe(a,b); 
b=0; 
a=1; 
$display(a,b); 
$write(a,b); 
$display(a,b); 
#1 b=1; 
end
initial
$monitor($time"ns: %b%b",a,b); 
Endmodule

Output:

01

10

1010

10

0ns: 10

1ns: 11

Question 12

not vs negate

(!) vs (~) vs not

Answer 12

• ~ is a bit-wise operator and returns the invert of the argument.
• ! is a logical operator and returns a single bit.
• not : Only used in SVA

reg [7:0] bit_wise, logic_op;
integer val = 1;
interger result;
initial begin
  bit_wise = ~8'hA1; // bit_wise == 8'h5E
  logic_op = !8'hA1; // logic_op == 8'b00
	result = ~val;   // result=11111111111111111111111111111110 
	                         //           = 0xFFFE
	                         // (interger converted to 32-bit logic)
	result = !val;   // result=0
	end
//*********************************************
sequence s_is_a;
@(posedge clk) a;
endsequence
property p_is_n_a;
not s_is_a;
endproperty
prop_name : assert propery(p_is_n_a);

Question 13

Enable dumping

Answer 13

initial begin
  $dumpfile("dump.vcd");
  $dumpvars;
end

Question 14

100 $finish;

vs
#100; $finish;
vs
repeat(10) @(posedge clk) $finish;
vs
repeat(10) @(posedge clk); $finish;

Question 15

$finish vs $exit vs $stop

Question 16

$finish argument

Answer 16

$finish can take arg of value :
* 0 : Prints nothing(default)
* 1 : Prints simulation time and location
* 2 : Prints simulation time, location, and statistics about the memory and central processing unit (CPU) time used in simulation