CISSP ch 9 Flashcards
AIS
Automated indicator sharing, initiative by the Department of Homeland Security (DHS) to facilitate the open and free exchange of indicators of compromise (IoCs) and other cyberthreat information between US federal government and the private sector in an automated and timely manner (“machine speed”)
IoC
indicators of compromise
Indicator = observable and a hypothesis about a threat
Observable = identified fact of occurrence, such as the presence of a malicious file, usually accompanied by a hash
STIX
Structured Threat Information eXpression, used in AIS to share threat indicators
TAXII
Trusted Automated eXchanged of Intelligence Information, used in AIS to share threat indicators
NCCIC
National Cybersecurity and Communications Integration Center
Multiprogramming
= Pseudo-simultaneous execution of two tasks on a single processor coordinated by the OS as a way to increase operational efficiency
= Batching or serializing multiple processes so that when one process stops to wait on a peripheral, its state is saved and the next process in line begins to process
= Causes delays for a single program, but total time to complete all tasks in a batch is reduced
Multitasking
= Handling two or more tasks simultaneously
= Cannot truly be performed by a single-core CPU
Multicore
= CPU is a chip containing multiple independent execution cores that can operate simultaneously and/or independently
Multiprocessing
= System that harnesses the power of more than one processor to complete the execution of a multithreaded application
Affinity
= When a multiprocessor system assigns or dedicates a process or execution thread to a specific CPU or core
Multithreading
= Permits multiple concurrent tasks to be performed within a single process
Thread
= a self-contained sequence of instructions that can execute in parallel with other threads that are of the same parent process
= switching between threads is more efficient than switching between multiple active processes/contexts
Ring 0
= OS Kernel/Memory
= Resident components
= Highest level of privilege, can access any resource, file or memory location
= Can preempt code running at any other ring
Ring 1
= Other OS components
Ring 2
= Where input-output (I/O) drivers and system utilities reside
= Able to access peripheral devices, special files and other resources that application and other programs cannot access directly
Ring 3
= User-level programs and applications
Rings for supervisory, kernel or privileged mode
= Rings 0 – 2 run in supervisory, kernel or privileged mode
Designed to give the OS access to the full range of instructions supported by the CPU
Only processes that are components of the OS itself are allowed to execute in this mode, for both security and system integrity purposes
Ring for user mode
= Ring 3 runs in user mode
Basic mode used by the CPU when executing user applications
CPU allows execution of only a portion of its full instruction set
System call
= When a process running in a higher-numbered ring asks a handler/driver in a lower-numbered ring for services they need
= Mediated-access model
Process / operating states
Ready, running, waiting, supervisory, stopped
Ready state
= Process is ready to resume or begin processing as soon as it is scheduled for execution
= Moves to running state
Running state / Problem state
= Process executes on the CPU and keeps going until it finishes, its time slice expires, or it is blocked for some reason
= Moves to ready state, waiting state or stopped state
Waiting state
= Process is ready for continued execution but is waiting for I/O to be serviced before it can continue processing
= Moves to ready state
Supervisory state
= Process must perform an action that requires privileges that are greater than the problem state’s set of privileges
E.g., modifying system configuration, installing device drivers, modifying security settings
Any function not occurring in the user mode or problem state
= Replaces running state when a process is run with higher-level privileges
Stopped
= When a process finishes or must be terminated
E.g., an error occurs, a required resource is not available or a resource request can’t be met
Problem state (OS mode)
= Associated with user mode, where privileges are low and all access requests must be checked against credentials for authorization before they are granted/denied
ROM
read-only memory = memory the system can read but can’t change (no writing)
POST
power-on self-test, contained in bootstrap
PROM
programmable read-only memory = chip’s contents aren’t burned in at the factory, and can instead be burned in by an end user. Once data is written to a PROM chip, no further changes are possible
EPROM
Erasable programmable read-only memory
UVEPROM
Ultraviolet Erasable programmable read-only memory = chips with a small window that, when illuminated with a special ultraviolet light, causes the contents of the chip to be erased, allowing end users to burn new information into the UVEPROM as if it had never been programmed before
EEPROM
Electronically erasable programmable read-only memory = uses electric voltage delivered to the pins of the chip to enforce erasure = e.g. Flash memory
RAM
random access memory = readable and writable memory that contains information a computer uses during processing = only retains its contents when power is continuously supplied to it, can only be used for temporary storage
Real memory / Main memory / Primary memory
= The largest RAM storage resources available to a computer
= Composed of a number of dynamic RAM chips, and must therefore be refreshed by the CPU on a periodic basis
Cache RAM
= Caches that improve performance by taking data from slower devices and temporarily storing it in faster devices when repeated use is likely
= Processor normally contains an onboard cache of extremely fast memory used to hold data on which it will operate, referred to L1, L2, L3 and L4 cache (L = level). L1 and L2 dedicated to a single processor core, L3 may be a shared cache between cores, some CPUs have L4, which may be located on the mainboard/motherboard or on the GPU
Dynamic RAM
= Uses series of capacitors, tiny electrical devices that hold a charge
= Because capacitors naturally lose their charge over time, CPU must spend time refreshing the contents of dynamic RAM to ensure that 1 bits don’t unintentionally change to 0 bits
= Cheaper and runs slower
Static RAM
= Uses a logical device known as a flip-flop, i.e., an on/off switch that must be moved from one position to another to change to a 0 to 1 or vice versa
= Maintains its contents unaltered as long as power is supplied and imposes no CPU overhead for periodic refresh operations
= More expensive and runs much faster
HDD
Hard disk drives
Register
Limited amount of onboard memory of a CPU directly accessible by the arithmetic logical unit when performing calculation or processing instructions = often 32 or 64 bits in size = part of the ALU itself and operates in lockstep with the CPU at typical CPU speeds
ALU
arithmetic logical unit = the brain of the CPU
Register adressing
= When the CPU needs information from one of its registers to complete an operation, uses a register address (e.g., register 1) to access its contents
Immediate adressing
= Way of referring to data that is supplied to the CPU as part of an instruction
= E.g. “Add 2 to the value in register 1”
Adding value 2 without need to retrieve that value from a memory location is immediate addressing
Direct adressing
= CPU is provided with an actual address of the memory location to access
= Address must be located on the same memory page as the instruction being executed
= More flexible than immediate addressing, since the contents of the memory location can be changed more readily than reprogramming the immediate addressing’s hard-coded data
Indirect adressing
= Memory address supplied to the CPU as part of the instruction doesn’t contain the actual value that the CPU is to use, but instead contains another memory address
= CPU reads the indirect address to learn the address where the desired data resides and then retrieves the actual operand (object) from that address
Base+Offset addressing
= Uses a value stored in one of the CPU’s registers or points as the base location from which to begin counting
Pointer
= A basic element or object used to store a memory address
= Holds the address of something stored in memory so that when the program reads the pointer, it is pointing to the location of the data actually needed by the application
Dereferencing
= Act of accessing a pointer to read that memory location
Race condition
= When a system or device tries to perform two or more operations at the same time
= Can cause a null pointer error in which an application dereferences a pointer that it expects to be valid is really null (or corrupted), resulting in a system crash
Secondary memory
Secondary memory = magnetic, optical or flash-based media or other storage devices that contain data not immediately available to the CPU. For the CPU to access data in secondary memory, data must first be read by the OS and stored in real memory
= All the long-term storage devices
= E.g., HDDs, SSDs, flash drives, magnetic tapes, CDs, DVDs and flash memory cards