Characteristics Of CPU Flashcards
Function of Control Unit
Coordinates activity between components and decode instructions.
Function of the Arithmetic Logic Unit
Responsible for logic and arithmetic calculations (+ - / *), logic, and shift operations.
What does the data bus do
Transmits data between instructions.
What does the address bus do
Carries the location of the address, where data is going from/to.
What does the control bus do
Transmits control signals e.g memory read/write/interrupts.
What does the Program Counter do?
Store memory address of the next instruction.
What does the Memory Address Register do?
Holds the address being read/written from.
What does the Memory Data Register do?
Holds the data that’s being read/written to/from.
What does the current Instruction Register do?
Holds the current instruction, decode into op-code and operand
What does the accumulator do?
General purpose register stores result from the ALU.
Explain the Fetch-Phase in the fetch-execute cycle.
1) Content is the PC are copies into MAR.
2) Memory is read to initiate a copy of the instruction word from memory to the MBR
3) The PC incremented, contains address to next instruction.
4) The instruction word is copied from the MBR into CIR. Instructions contain two parts: opcode and operand.
What is the op-code?
Instruction
What is the operand?
To perform the operation on.
Explain what happens in the Execute-Phase?
1) The opcode instruction in the CIR is decoded into simple operations such as ADD, STORE, and COMPARE.
2) The instructions in the CIR is executed; if the result needs to be committed by memory the address is held in the MAR
3) Unless instructions is stop the cycle is repeated
What are the factors that affect performance
1) Multiple Cores
2) Cache Memory
3) Clock Speed
4) Bus width, words
What is Pipelining
Completing the fetch-execute cycle in three separate phases instructions simultaneously.
What is the stored programme concept
1) Programs needs to be held in main memory to help executed in a processor
2) The instructions is fetched at a time decoded and executed sequentially
3) The sequence of instructions can be changed by a conditional or unconditional jump in instructions
Von Neumann Architecture
• Instructions and data are stored in a common main memory and transferred by a single bus.
• Cheaper to develop as control unit is easier to design.
• Programs can be optimised in size
• Good for general purpose.
Harvard Architecture
• Program and dats and stored in separate main memory and transferred by two separate buses.
• Quicker execution as data and instructions can be fetched in parallel
• Memories can be different sizes which can make efficient use of space.
• Hardware connections expensive: have two buses.
• Harvard principles can be used with specialist embedded systems.
Contemporary Processing
• Combination of Von Neumann architecture and Harvard
• Von Neumann used when working with data and instructions in main memory Harvard Architecture to divide cache into instruction cache and data cache.
Assembly Language
• Assembly code uses mnemoics to represent instructions: it’s a simplified way of writing machine code
• The instructions is divided into operand and op-code in Current Instruction Register.
RISC
• Reduced Instruction Set Computers
• Have a small instruction set.
• Each instruction is one line of machine code and takes one clock cycle.
CISC
- Complex Instruction Set Computers
- Have a large instruction set.
- Used in microcontrollers and embedded systems.
RISC vs CISC
RISC
- The complier has to do more work translating high level code into machine code
- More RAM required to store the code.
- Pipelining possible since each instruction takes one clock cycle.
CISC
- The complier can do less work then translating high level code into machine code.
- Less RAM is required since the code is shorter
- Many specialized instructions are made in only a few of them are used.
