chapter2

Question 1

Registers

Answer 1

Program counter- adress of the next instruction to be fetched
instuction register-adress of the current instruction to be executed
flag- Shift bit, binary operation
stack pointer-adress of the stack
General Purpose Register-data register,adress register
specialities-segmentregister

Question 2

fetch-decode-execute

Answer 2

The computer fetches the next instruction to be executed. the address is given by pc. it reads the instruction from memory and load to ir
the cpu decodes it what operationis required and what operand is needed
then execute - and rewrite to memory
pc incremented

Question 3

RISC

Answer 3

-smaller-simpler as CISC archtichture
-Pipeline friendly-simpler instruction pipelinre- higher speed clock- executed in a fixed number of clock cycles-predictable
-Register-rich: RISC -large number of general purpose registers, faster access to data and reducing the need to access memory
4.compiler friendly-better performance
5. load/store architechture
6.less circuit-cheaper

Question 4

cisc

Answer 4

1.Rich instruction set- larger and more complex instruction. access memory directly
2.Efficient Memory Access-instructions-operate directly on memory, reducing the need for explicit load and store , compact code and lower memory
3.less code overhead

Question 5

pipelines problems

Answer 5

traffic
idle

Question 6

Nachteil from parellel pipelines

Answer 6

Not all instructions are paralelable
more pipeline more silizium

Question 7

superscalar

Answer 7

parallel of slower units
instructions fetch- fetch all instructions
instruction decode- to determine what the type and operations
instructions issue- analyse which can be done parallel
execution -dispatch in different sectors
parallel execution

Question 8

vectorrechner

Answer 8

single instruction for different data

Question 9

utf-8

Answer 9

2^31-backward compatible with asci

Question 10

Access of devices

Answer 10

special Cpu instruction
memory mapped io
dma
operation program
- no direct access
special os function

Question 11

io ports

Answer 11

port-5 register
status regiser-read only (error, instruction executed, ready to be read)
control register-full duplex,half duplex,parity check
command register-cpu send to the controller
data in register-
data in register- data can be read from controller
data out register - data can be sent

Question 12

Different address-

Answer 12

accces is only controlled by th os
cpu must regulate access

Question 13

same addres

Answer 13

advantage-accesrightprotection through seiten
efficient read and manipulate
direct access through c/c++
problemm-complicate busarchitechture/ disable caching