Chapter 9 - Main Memory Flashcards
What is memory central to?
Memory is central to the operation of a modern computer system and consists of a large array of byes, each with its own address.
Describe one way to allocate an address space to each process.
One way to allocate an address space to each process is through the use of base and limit registers. The base register holds the smallest legal physical memory address, and teh limit specifies the size of the range.
When can binding symbolic addresses to actual physical addresses occur?
during:
1. compile
2. load
3. execution time
What is an address generated by the CPU?
An address generated by the CPU is known as a logical address, which the memory management unit (MMU) translates to a physical address in memory.
Mention one approach to allocate memory.
One approach to allocating memory is to allocate partitions of contiguous memory of varying sizes. These partitions may be allocated based on the three possible strategies:
1. first fit
2. best fit
3. worst fit
What do modern operating systems use to manage memory?
Modern operating systems use paging to manage memory. In this process, physical memory is divided into fixed-sized blocks called frames and logical memory into blocks of the same size called pages.
What happens when paging is used?
When paging is used, a logical address is divided into two parts: a page number and a page offset. The page number servers as an index into a preprocess page table that contains the frame in the physical memory that holds the page. The offset is the specific location in the frame being referenced.
What is a translation look-aside buffer (TLB)?
A translation look-aside buffer (TLB) is a hardware cache of the page table. Each TLB entry contains a page number and its corresponding frame.
What does using a TLB in address translation involve?
Using a TLB in address translation for paging systems involves obtaining the page number from the logical address and checking if the frame for the page is in the TLB. If it is, the frame is obtained from the TLB. If the frame is not present in the TLB, it must be retrieved from the page table.
What does hierarchical paging involve?
Hierarchical paging involves dividing a logical address into multiple parts, each referring to different levels of page tables. As addresses expand beyond 32 bits, the number of hierarchical levels may become large. Two strategies that address this problem are hashed page tables and inverted page tables.
What does swapping do?
Swapping allows the system to move pages belonging to a process to disk to increase the degree of multiprogramming.
How many levels of page tables does the intel 32-bit architecture have?
The Intel 32-bit architecture has two levels of page tables and supports either 4-KB or 4-MB page sizes. This architecture also supports page-address extension, which allows 32-bit processors to access a physical address space larger than 4 GB. The x86-64 and ARMv9 architectures are 64-bit architectures that use hierarchical paging.
