Chapter 6 - Memory Hierarchy Flashcards
the locality principle stating that if a data location is referenced then it will tend to be referenced again soon
Temporal locality
the locality principle stating that if a data location is referenced, data locations with nearby addresses will tend to be referenced soon
Spatial locality
a structure that uses multiple levels of memories, as the distance from the processor increases, the size of the memories and the access time both increase
Memory hierarchy
the minimum unit of information that can be either present or not present in a cache
Block (or line):
the fraction of memory accesses found in a level of the memory hierarchy
Hit rate
the fraction of memory accesses not found in a level of the memory hierarchy
Miss rate
the time required to access a level of the memory hierarchy, including the time needed to determine whether the access is a hit or miss
Hit time
the time required to fetch a block into a level of the memory hierarchy from the lower level, including the time to access the block, transmit it from one level to the other, insert it in the level that experienced the miss, and then pass the block to the requestor
Miss penalty
one of thousands of concentric circles that make up the surface of a magnetic disk
Track
one of the segments that make up a track on a magnetic disk; the smallest amount of information that is read or written on a disk
Sector
the process of positioning a read/write head over the proper track on a disk
Seek
also called rotational delay. The time required for the desired sector of a disk to rotate under the read/write head; usually assumed to be half the rotation time
Rotational latency
a cache structure in which each memory location is mapped to exactly one location in the cache
Direct-mapped cache
a field in a table used for a memory hierarchy that contains the address information required to identify whether the associated block in the hierarchy corresponds to a requested word
Tag
a field in the tables of a memory hierarchy that indicates that the associated block in the hierarchy contains valid data.
Valid bit
a request for data from the cache that cannot be filled because the data are not in the cache
Cache miss
a scheme in which writes always update both the cache and the next lower level of the memory hierarchy, ensuring that data are always consistent between the two
Write through
a queue that holds data while the data are waiting to be written to memory
Write buffer
a scheme that handles writes by updating values only to the block in the cache, then writing the modified block to the lower level of the hierarchy when the block is replaced
Write-back
a scheme in which a level of the memory hierarchy is composed of two independent caches that operate in parallel with each other with one handling instructions
Split cache
a cache structure in which a block can be placed in any location in the cache
Fully associative cache
a cache that has a fixed number of locations (at least two) where each block can be placed
Set-associate cache
a replacement scheme in which the block replaced is the one that has been unused for the longest time
Least recently used (LRU)
a memory hierarchy with multiple levels of caches, rather than just a cache and main memory
Multilevel cache
the fraction of references that miss in all levels of a multilevel cache
Global miss rate
the fraction of references to one level of a cache that miss, used in multilevel hierarchies
Local miss rate
A code that enables the detection of an error in data, but not the precise location and, hence, correction of the error.
Error detection code
a technique that uses memory as a “cache” for secondary storage
Virtual memory
an address in main memory
Physical address
a set of mechanisms for ensuring that multiple processes sharing the processor, memory, or I/O devices cannot interfere, intentionally or unintentionally, with one another by reading or writing each other’s data. The mechanisms also isolate the operating system from a user process.
Protection
an event that occurs when an accessed page is not present in main memory
Page fault
an address that corresponds to a location in virtual space and is translated by address mapping to a physical address when memory is accessed
Virtual address
also called address mapping. The process by which a virtual address is mapped to an address used to access memory
Address translation
a variable size address mapping scheme in which an address consists of two parts: a segment number, which is mapped to a physical address, and a segment offset
Segmentation
the table containing the virtual to physical address translations in a virtual memory system. The table, which is stored in memory, is typically indexed by the virtual page number; each entry in the table contains the physical page number for that virtual page if the page is currently in memory.
Page table
the space on the disk reserved for the full virtual memory space of a process
Swap space
also called use bit or access bit. A field that is set whenever a page is accessed and that is used to implement LRU or other replacement schemes
Reference bit
a cache that keeps track of recently used address mappings to try to avoid an access to the page table
Translation-lookaside buffer (TLB):
a cache that is accessed with a virtual address rather than a physical address
Virtual addressed cache
a situation in which two addresses access that same object, it can occur in virtual memory when there are two virtual addresses for the same physical page
Aliasing
a cache that is addressed by a physical address
Physically addressed cache
also called kernel mode. A mode indicating that a running process is an operating system process
Supervisor mode
a special instruction that transfers control from user mode to a dedicated
location in supervisor code space, invoking the exception mechanism in the process
System call
a changing of the internal state of the processor to allow a different process
to use the processor that includes saving the state needed to return to the currently executing process
Context switch
also called interrupt enable. A signal or action that controls whether the process responds to an exception or not, necessary for preventing the occurrence of exceptions during intervals before the processor has safely saved the state needed to restart
Exception enable
an instruction that can resume execution after an exception is resolved without the exception’s affecting the result of the instruction
Restartable instruction
increasing utilization of a processor by switching to another thread when one thread is stalled.
Hardware multithreading
includes the program counter, the register state, and the stack. It is a lightweight process; commonly share a single address space, processes don’t
Thread
includes one or more threads, the address space, and the operating system state.
Process
a version of hardware multithreading that implies switching between threads after every instruction
Fine-grained multithreading
a version of hardware multithreading that implies switching between threads only after significant events, such as a last-level cache miss.
Coarse-grained multithreading
a version of multithreading that lowers the cost of multithreading by utilizing the resources needed for multiple issue, dynamically scheduled microarchitecture
Simultaneous multithreading (SMT)
a multiprocessor in which latency to any word in main memory is about the same no matter which processor request the access
Uniform memory access (UMA)
a type of single address space multiprocessor in which some memory accesses are much faster than others depending on which processor asks for which word
Nonuniform memory access (NUMA)
the process of coordinating the behavior of two or more process, which may be running on different processors.
Synchronization
a synchronization device that allows access to data to only one processor at a time
Lock
a function that processes a data structure and returns a single value
Reduction
an API for share memory multiprocessing in C, C++, or Fortran that runs on UNIX and Microsoft platforms. It includes compiler directives, a library, and runtime directives
OpenMP
Communication between multiple processors by explicitly sending and receiving information
Message passing
a routine used by a processor in machines with private memories to pass a message to another processor
Send message routine
a routine used by a processor in machines with private memories to accept a message from another processor
Receive message routine
Collection of computers connected via I/O over standard network switches to form a message passing multiprocessor
Clusters
rather than selling software that is installed and run at customers’ own computers, software is run at a remote site and made available over the Internet typically via a Web interface to customers. charged based on use versus ownership
Software as a service (SaaS)
informally, the peak transfer rate of a network; can refer to the speed of a single link or the collective transfer rate of all links in the network
Network Bandwidth
the bandwidth between two equal parts of multiprocessor. This measure is for a worst case split of the multiprocessor
Bisection bandwidth
a network that connects processor memory nodes by supplying a dedicated communication link between every node
Fully connected network
a network that supplies a small switch at each node.
Multistage network
a network that allows any node to communicate with any other node in one pass through the network
Crossbar network
an I/O scheme in which portions of the address space are assigned to I/O devices, and reads and writes to those addresses are interpreted as commands to the i/O device.
Memory-mapped I/O
a mechanism that provides a device controller with the ability to transfer data directly to or from the memory without involving the processor
Direct memory access (DMA)
an I/O scheme that employs interrupts to indicate to the processor that an I/O device needs attention
Interrupt-driven I/O
a program that controls an I/O device that is attached to the computer
Device driver
the process of periodically checking the status of an I/O device to determine the need to service the device
Polling
an organization of disks that uses an array of small and inexpensive disks so as to increase both performance and reliability
Redundant arrays of inexpensive disks (RAID)
no redundancy, widely used
RAID0
(Mirroring) EMC, HP(Tandem), IBM
RAID1
(Error detection and correction code) unused
RAID2
(bit interleaved parity) storage concepts
RAID3
block-interleaving parity, network appliance
RAID4
Distribution block-interleaved parity, widely used
RAID5
P+Q redundancy, recently popular
RAID6
