Chapter 4 - The Processor Flashcards
What factors determine CPU performance?
Instruction Count, Cycles Per Instruction (CPI), Cycle Time
Explain the function of combinational and sequential elements in a processor.
Combinational Elements: These operate on data where the output is a function of the input. Examples include:
AND Gate: Y = A & B
Adder: Y = A + B
Multiplexer: Y = S ? I1 : I0
ALU (Arithmetic/Logic Unit): Y = F(A, B), where F is the function performed (e.g., add, subtract).
Sequential Elements: These store information and update their output based on clock signals. Examples include:
Register: Stores data and updates the value on the clock edge.
Register with Write Control: Updates only on the clock edge when the write control input is 1.
What are the components of a basic MIPS datapath?
Instruction Memory: For fetching instructions.
Register File: For reading and writing register values.
ALU: For performing arithmetic and logical operations.
Data Memory: For load and store operations.
Multiplexers: For selecting inputs based on the instruction type.
Control Unit: For generating control signals based on the instruction type.
Explain the concept of pipelining in processors.
Pipelining improves processor performance by overlapping the execution of multiple instructions. Each instruction is divided into stages, and different stages of multiple instructions are processed simultaneously. The stages typically include:
Instruction Fetch (IF)
Instruction Decode (ID)
Execute (EX)
Memory Access (MEM)
Write Back (WB)
Pipelining increases instruction throughput but can introduce hazards that need to be managed.
What are the types of hazards in pipelining, and how can they be mitigated?
Structural Hazards: Occur when two instructions require the same hardware resource simultaneously. Mitigated by duplicating resources or using separate instruction and data memories.
Data Hazards: Occur when instructions depend on the results of previous instructions. Mitigated by forwarding (bypassing) data from one pipeline stage to another.
Control Hazards: Occur due to branch instructions that affect the flow of control. Mitigated by branch prediction, stalling, or using techniques like delayed branching.
What are the techniques used for branch prediction in pipelined processors?
Static Prediction: Based on typical branch behavior, such as predicting backward branches (loops) as taken and forward branches (if statements) as not taken.
Dynamic Prediction: Based on the actual runtime behavior of branches, using hardware to track the history of branch outcomes and predict future behavior based on trends.
These techniques aim to minimize the performance penalty of control hazards by guessing the branch outcome.
Explain the necessity of pipeline registers between stages in a pipelined datapath.
Pipeline registers are essential in a pipelined datapath because they hold the intermediate data and control information between the stages of the pipeline. Without these registers, it would be impossible to maintain the flow of multiple instructions simultaneously, as the data required for each stage would not be preserved across clock cycles. These registers ensure that each stage of the pipeline can operate independently and concurrently, thus improving the overall throughput of the processor. For example, in the MIPS pipeline, registers are placed between the Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB) stages to hold relevant data such as instruction codes, operand values, and computed addresses.
What are data hazards in pipelined processors and how can they be resolved using forwarding?
A data hazard arises if an instruction depends on the result of a previous instruction that has not yet completed its execution. There are three types of data hazards:
RAW (Read After Write): A subsequent instruction needs to read a register before a previous instruction writes to it.
WAR (Write After Read): A subsequent instruction writes to a register before a previous instruction reads it.
WAW (Write After Write): Two instructions write to the same register in sequence.
Forwarding (or data bypassing) resolves RAW hazards by routing the output of an instruction directly to the input that needs it, without waiting for it to be written back to the register file.
Describe the cycle-by-cycle flow of instructions through the pipelined datapath and explain the concept of a “single-clock-cycle” pipeline diagram.
The cycle-by-cycle flow of instructions allows multiple instructions to be processed simultaneously in different stages, thus increasing the instruction throughput.
A “single-clock-cycle” pipeline shows the state of the pipeline in a single clock cycle, showing which resources are being used by which instruction at that moment. For instance, if we have three instructions (I1, I2, I3) in different stages, the diagram might show I1 in the Execute stage, I2 in the Decode stage, and I3 in the Fetch stage.
Explain the steps involved in executing a load instruction in a pipelined processor.
Instruction Fetch (IF): The load instruction is fetched from the instruction memory using the Program Counter (PC).
Instruction Decode (ID): The instruction is decoded to determine the source register and the offset for the address calculation. The base address is read from the register file.
Execute (EX): The effective address for the load is calculated by adding the base address and the offset.
Memory Access (MEM): The calculated address is used to access the data memory, and the data is read from the memory location.
Write Back (WB): The data read from memory is written back to the destination register in the register file.
This sequence ensures that the load instruction correctly retrieves data from memory and places it into the specified register.
Describe how load-use data hazards are detected and managed.
A load-use data hazard occurs when an instruction tries to use data by an instruction before the data is available. To detect this hazard, the processor checks if an instruction in the ID stage is trying to read a register in the EX stage.
Inserting a bubble into the EX stage.
Preventing the update of the PC and IF/ID.
Use stall to complete its memory access and foward data correctly.
Explain how branch hazards affect the pipeline and describe the role of dynamic branch prediction in mitigating branch penalties.
Branch hazards occur because the outcome of a branch instruction is not known until it is in the EX or MEM stage, leading to uncertainty about which instruction to fetch next. If the branch is taken, instructions that were fetched based on the assumption that the branch was not taken must be flushed from the pipeline, causing a stall and reducing performance.
Dynamic branch prediction mitigates branch penalties by predicting the outcome of branches based on historical data stored in a branch prediction buffer. This buffer is indexed by the addresses of recent branch instructions and stores whether the branches were taken or not. When a branch instruction is encountered, the processor checks the prediction buffer and speculatively fetches the next instruction based on the predicted outcome. If the prediction is correct, the pipeline continues without interruption. If the prediction is incorrect, the pipeline is flushed, and the correct instructions are fetched, updating the prediction buffer for future accuracy.
Discuss the role and design of a branch target buffer in modern processors.
BTB stores the target addresses of recently executed branches. It improves performance by reducing the branch penalty to a single cycle for taken branches and potentially zero cycles for predicted branches.
Explain the concept of an exception in a pipeline. How is it similar to a control hazard?
An exception in when an unexpected event requires special handling.
This is similar to a control hazard because both disrupt the normal flow of instructions.
What are restartable exceptions?
Restartable exceptions allow the faulting instruction to be flushed and then re-executed from scratch.
