Chapter 4 Flashcards

1
Q

it is a representation of the state of voltage variables.

A

Logic level

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2
Q

Logic “0” and logic “1” can be
represented by —————-

A

voltage levels

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3
Q

In logic circuits, logic 1 is represented by ———————— which is the maximum voltage level to represent logic 1. Above this voltage level is considered as ——————————- level. On the other hand a voltage from ————————- represents logic “0”.

A
  • 2 volts (min) to 5 volts
  • invalid voltage or illegal logic
  • zero(0V) to 0.8volts
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4
Q

Voltage levels in between the maximum voltage allowed for logic 0 and the minimum voltage to represent logic 1 is Invalid, this is called the ————————

A

Invalid Voltage Range

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5
Q

It is a means for describing how logic circuits output depends on the logic levels present at the circuits inputs.

A

Truth Table

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6
Q

It also contains the list of possible combinations of the inputs and the corresponding output for that logic combination.

A

Truth Table

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7
Q

A tool for the analysis and design of digital systems.

A

Boolean Algebra

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8
Q

It is a relatively simple mathematical tool that allows us to describe the relationship between a logic circuits output(s) and its inputs as an algebraic equation (a Boolean expression).

A

Boolean Algebra

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9
Q

Boolean algebra is an —————- that was developed by ———————–.

A

algebraic system, George Boole in 1854

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10
Q

performs the Boolean NOT operation. When the input is Logic 0, the output becomes Logic 1; when the input is logic 1, the output becomes logic 0.

A

The Inverter (NOT Gate)

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11
Q

The NOT operation (complement) is shown with an ———- on the variable you used (sometimes prime ‘ is used).

The Inverter (NOT Gate)

A

over-bar

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12
Q

One application of this function is when you need to form the 1’s complement of a binary number.

A

The Inverter (NOT Gate)

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12
Q

produces a Logic 1 output when all inputs are also Logic 1; otherwise, the output is Logic 0.

A

AND gate

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13
Q

is usually shown with a dot (.) between the variables but it may be implied (no dot).

A

AND operation

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14
Q

The AND operation is used in computer programming as a ——————–. If you want to retain certain bits of a binary number but reset the other bits to 0, you could set a mask with 1’s in the position of the retained bits.

A

selective mask

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15
Q

produces a Logic 1 output if any input is logic 1; if all inputs are logic 0, the output is Logic 0.

A

OR gate

16
Q

shown with a plus sign (+) between the variables

A

OR gate

17
Q

The OR operation can be used in computerprogramming to set certain bits of a binary number to 1.

A

computer programming

18
Q

can have two or more inputs

A

NAND gate

19
Q

The output will be logic 0 only when all the inputs are logic 1. Conversely, the output will be logic 1 when any or all of the inputs are logic 0.

A

NAND gate

20
Q

performs two functions, AND and NOT.

A

NAND gate

21
Q

is shown with a dot between the variables and an overbar covering them.

A

NAND operation

22
Q

The NAND gate can replace the functions of all the basic gates, that’s why it is called a

A

“universal” gate.

23
Q

is an OR gate followed by an inverter.

A

NOR gate

24
Q

will have a logic 1 output only when all the inputs are logic 0.

A

NOR gate

25
Q

is shown with a plus sign (+) between the variables and an overbar covering them.

A

NOR operation

26
Q

is a modified OR gate that produces a logic 1 output when only one of the inputs is logic 1. You will often see the abbreviation X-OR used to identify this gate.

A

eXclusive OR (XOR) gate

27
Q

When both inputs are logic 1 or when both inputs are logic 0, the output is equal to logic 0.

A

eXclusive OR (XOR) gate

28
Q

is nothing more than an X-OR gate followed by an inverted gate at the output.

A

exclusive NOR (X-NOR) gate

29
Q

It produces logic 1 output when all inputs are either logic 1 or logic 0.

A

exclusive NOR (X-NOR) gate

30
Q

will produce logic 1 when both inputs are the same. One of the applications of this logic gate is for comparing the two binary signals.

A

XNOR gate

31
Q

Two major fixed function logic families are —- and ——–

A
  1. TTL
  2. CMOS
32
Q

TTL and CMOS. A third technology is ———-, which combines the first two.

A

BiCMOS

33
Q

2 Packaging for fixed function logic

A
  1. DIP package
  2. SOIC package