chapter 4 Flashcards
What does the Happens Before Guarantee for Reads of volatile Variables state?
A read of a volatile variable will happen before any subsequent reads of volatile and non-volatile variables
What can happen if two or more threads are sharing an object without proper synchronization or volatile declarations?
Updates to the shared object made by one thread may not be visible to other threads.
What happens if a thread running on CPU one changes the shared object in its CPU cache before flushing it back to main memory?
The changed version of the shared object is not visible to threads running on other CPUs.
Give an example of a race condition (train ticket booking)
If two passengers try to book the only available ticket at the same time without synchronization, both might end up booking tickets, causing a problem.
What are special hardware instructions that allow us to modify the content of a word or swap the contents of two words atomically?
Test-and-Set instruction and Compare-and-Swap instruction are special hardware instructions.
How can you solve the problem of race condition with volatile variables?
You can use a Java synchronized block to guarantee only one thread can enter a given critical section of the code at any given time.
Imagine thread A reads the variable count into its CPU cache, while thread B does the same into a different CPU cache. What happens if both threads increment the count?
The variable count will be incremented twice, once in each CPU cache.
Do volatile variables guarantee solving the synchronization problem for race condition?
No, volatile variables do not guarantee solving the synchronization problem for race condition.
What is the purpose of the AtomicBoolean variable in the counter example?
The AtomicBoolean variable is used as a lock to provide synchronization.
What is the purpose of a memory barrier instruction?
To ensure that all loads and stores are completed before any subsequent load or store operations are performed.
What can a memory barrier instruction prevent?
Reordered instructions and ensure store operations are completed in memory and visible to other processors before future load or store operations are performed.
What can happen in multithreading applications without proper synchronization?
Reorder instruction problems, where instructions can be reordered leading to unexpected behavior.
What do computer architectures provide to ensure memory modifications are visible to threads running on other processors?
Memory barriers or memory fences.
Why can’t kernel developers make assumptions about memory modifications on a shared-memory multiprocessor?
Memory models vary by processor type.
What is a weakly ordered memory model?
Where a memory modification of one processor may not be immediately visible to all other processors.