Chapter 3: Sequential Logic Systems

Question 1

How is a sequential logic system different to a logic system?

Answer 1

In a sequential logic system, the output also depends on past input states. However, a sequential system has some form of ‘memory’ of what happened previously.

Question 2

How does a sequential logic system use outputs to influence the input?

Answer 2

A sequential logic system uses feedback to allow the current output state to influence future input states.

Question 3

What is a ‘Flip-flop’ or a ‘Bistable’ ?

Answer 3

It has two stable states (hence ‘bistable’) and it flips (or flops) between the two. It is a sub-system with two input terminals and two output terminals, usually

Question 4

What is the most common type of Flip-flop?

Answer 4

The Set-Reset latch

Question 5

Describe the inputs and outputs of a Set-reset latch (not s, not r)

Answer 5

Both inputs have a ‘bar’ above them, indicating that they are ‘active low’ inputs. This means that they are activated when the input signal is logic 0. Both outputs are labelled Q but one Q is the inverse of the other. The outputs should always be at opposite logic levels. When output Q is logic 1, it is ‘set’. When it is logic 0, it is ‘reset’.

Question 6

The Not s, not R latch can be implemented using what logic gate?

Answer 6

NAND gate

Question 7

Give the truth table for a NAND gate equivalent of a Not S, Not R latch

Answer 7

Not S= B Not R=A
B A Q Ǭ
0 1 1 0
1 1 1 0
1 0 0 1
1 1 0 1
0 0 1 1

Question 8

Explain ‘state 1’ of a not S, not R latch where S is 0 and R is 1

Answer 8

The logic 0 at the not S input sets the the output. The input is active low

Question 9

Explain ‘state 2 and 4’ of a not S, not R latch, where not S is logic 1 and not R is logic 1

Answer 9

When both inputs are logic 1, the outputs are unchanged from the
previous state. This is known as the latching combination.

Question 10

Explain ‘state 3’ of a flip flop where not S is logic 1 and not R is logic 0

Answer 10

the reverse of state 1 – logic 0 at the not R input resets the output.

Question 11

Explain ‘state 5’ of a flip flop, where not S and not R are both loic 0

Answer 11

This is the problem state. Q and not Q are meant to be opposite states but, in this case they are the same.

Question 12

State the limitations of a the simple latch

Answer 12

1. The Q and Q outputs both sit at logic 1 when both inputs are at logic 0.
2. The inputs are active-low.
3. Changes in the outputs occur immediately in response to changes in the inputs.

Question 13

How can the limitation of ‘changes in the outputs occur immediately in response to changes in the inputs’ the simple latch be overcome?

Answer 13

By using an additional unit known as a clock input.

Question 14

How can the limitation of ‘The inputs are active-low’ be overcome on a not S, not R latch?

Answer 14

By using an additional unit known as a clock input as well as 2 additional NAND gates which are fed into the input of the simple latch

Question 15

Explain how a clocked S-R latch solves 2 limitations of a simple latch

Answer 15

The Q and not Q outputs change only when: the clock input is logic 1 (overcoming limitation 3), input S (or R) is logic 1 (overcoming limitation 2).

Question 16

Use of a clock input improves the performance of the latch by ensuring that what happens?

Answer 16

Data transfer when a clock pulse is present

Question 17

What is level triggering?

Answer 17

the outputs can change whenever the clock input is at a specific logic level.

Question 18

What is edge triggering

Answer 18

where the output can change only when the clock input is changing (rising edge/ falling edge)

Question 19

State one way in which edge triggering can be achieved

Answer 19

Using a transition gate

Question 20

What is propagation delay?

Answer 20

The time taken for the output of a logic gate to change after the input changes