Chapter 2: ARM Processor Fundamentals

Question 1

What is ARM core dataflow?

Answer 1

Uses a load/store architecture.

• Processor begins the execute instructions.
• Data are placed in register file (storage made of 32-bit registers.
• Register file buses to ALU or MAC and compute results.
• Load/store instructions use the ALU to generate address held in the address register.
• Load/store instructions the incrementor updates the address register before the ore reads/writes the next register value from or to the next sequential memory.
• Processor continues executing instructions until an exception or interrupt changes the flow.

Question 2

Instruction set

Answer 2

list of operation/instruction that the hardware understands.

Question 3

sign extend

Answer 3

converts signed 8-bit and 16-bit numbers to 32-bit values as they read from memory and placed in a register.

Question 4

How does address register work?

Answer 4

if I want to read something for the memory, it comes from the address register.

Question 5

how many register are in LEGv8?

Answer 5

32 registers

Question 6

how many register are in LEGv8?

Answer 6

32 registers

Question 7

What are registers?

Answer 7

Register is a storage which stores either data or an address

Question 8

Program status registers

Answer 8

CPSR (Current Program Status Register) and SPSR (Saved Program Status Register)

Used to monitor and control internal operations. CPSR is a dedicated 32-bit register and resides in the register file.

Question 9

How many modes can the process can operate, and what are them?

Answer 9

7

Question 10

What is the control field?

Answer 10

Control field contains the processor mode, state, and interrupt mask bits. The flags field contains the condition flags.

Question 11

Condition flags ‘S’

Answer 11

Updated by comparisons and the resultant of ALU operations.

Question 12

Conditional Execution

Answer 12

Processor compares the condition attribute with the condition flags in cpsr. If they match, then execute instructions; otherwise ignore instructions.

Question 13

What is the three-stage Pipeline?

Answer 13

Fetch (load an instruction from memory)
Decode (identifies the instruction to be executed)
Execute (processes the instruction and writes the result back to the register)

Pipeline speeds up execution by fetching the next instruction while other instructions are being decoded and executed.

Question 14

load

Answer 14

fetch from memory, and places in regiester

Question 15

What is a vector table

Answer 15

When exception/interrupt occurs, the processor sets to PC to a specific memory address.