Chapter 18 Hardware And Virtual Machines Flashcards
CISC
A complex instruction set computer designed to carry out a given task with as few lines of assembly code as possible
CISC processor is based on a complex instruction which needs to be converted by the processor into a number of sub-instructions to carry out the required operation
fixed length instructions
the amount of memory it will consume is fixed (e.g: 16 bits)
variable length instructions
can take as much space as it wants
hardwired control unit
uses logic circuits flip flop
programmable control unit
uses programs, code will compile, run and generate output
features of CISC
- Fewer instructions
- Simpler instructions
- Small number of instruction formats
- Single - Cycle instructions whenever possible
- Fixed - length instructions
- Only load and store instructions to address memory
- Fewer addressing modes
- Multiple register sets
- Hard-wired control unit
- Pipelining is easier
larger number of instructions + more complex fewer registers => most processing is done in memory many instruction formats requires more complex circuit has more addressing modes makes less use of RAM poor pipelineability uses multicycle and variable length instruction has programmable control unit
RISC
A single instruction is simpler, requiring minimal loading of data from memory
- Reduced instruction set computer less instruction => Better performance from the processor (does not need to break complex instructions) assembly code is broken into a number of single cycle instructions
features of RISC
fewer instructions better pipelineablity many registers simpler instructions few instruction formats usually uses single cycle instructions uses fixed length instructions less complex circuit fewer addressing modes makes more use of RAM has hardwired control unit
pipelining
instruction level parallelism => multiple operations are performed in a single cycle execution of an instruction is split into number of stages when first stage for an instruction is completed the first stage of the next instruction can start executing another instruction can start executing before the previous one is finished processing of a number of instructions can be done simultaneously
alternate method to pipelining
content of five stages can be stored in register then the processor can be restored to its previous state once the interrupt has been serviced
flynn’s classification
computer architecture based on number of instructions and data instruction stream: sequence of instructions executed by the processing unit data stream: sequence of data or temporary result called by instruction stream
single instruction single data (SISD)
only one processor processor executes one set of instructions on one set of data
single instruction multiple data (SIMD)
uses many processors each processor has several ALUs each ALU executes the same set of instruction on a different set of data at the same time
multiple instruction single data (MISD)
several processors each processor executes a different set of instructions on one set of data at the same time
multiple instruction multiple data (MIMD)
several processors each processor executes a different set of instructions each processor operates on a different set of data
