Chapter 18 Boolean Algebra and Logic Circuits Flashcards
State the ‘Annulment’ Law for both AND/OR
AND Version • A ^ 0 = 0 • A . 0 = 0 OR Version • A v 1 = 1 • A + 1 = 1
State the ‘Identity’ Law for both AND/OR
AND Version • A ^ 1 = A • A . 1 = A OR Version • A v 0 = A • A + 0 = A
State the ‘Idempotent’ Law for both AND/OR
AND Version • A ^ A = A • A . A = A OR Version • A v A = A • A + A = A
State the ‘Complement’ Law for both AND/OR
AND Version • A ^ ¬A = 0 • A . ¬A = 0 OR Version • A v ¬A = 1 • A + ¬A = 1
State the ‘Double Negation’ Law
¬(¬A) = A
State the ‘Associative’ Law for both AND/OR
AND Version • (A ^ B) ^ C = A ^ (B ^ C) • (A . B) . C = A . (B . C) OR Version • (A v B) v C = A v (B v C) • (A + B) + C = A + (B + C)
State the ‘Commutative’ Law for both AND/OR
AND Version • A ^ B = B ^ A • A . B = B ^ A OR Version • A v B = B v A • A + B = B + A
State the both version of the ‘Distributive’ Law
First Version • A ^ (B v C) = (A ^ B) v (A ^ C) • A . (B + C) = (A . B) + (A . C) Second Version • A v (B ^ C) = (A v B) ^ (A v C) • A + (B . C) = (A + B) . (A + C)
State the both version of the ‘Absorptive’ Law
First Version • A ^ (B v C) = A • A . (B + C) = A Second Version • A v (B ^ C) = A • A + (B . C) = A
State the both version of the ‘De Morgan’s’ Law
First Version • ¬(A ^ B) = ¬A v ¬B • ¬(A . B) = ¬A + ¬B Second Version • ¬(A v B) = ¬A ^ ¬B • ¬(A + B) = ¬A . ¬B
Youtube Video with logic circuit representation of all boolean algebra laws and Image of all Boolean Algebra Laws
- YT vid: https://www.youtube.com/watch?v=EPJf4owqwdA
* Image: https://drive.google.com/file/d/1AERcZmNuuCFX6kuvxOqfS4I9dY8YbwnY/view?usp=sharing
What does ‘Boolean Addition’ correspond to in terms of a singular logic gate
Truth Table of an OR Gate
What does ‘Boolean Multiplication’ correspond to in terms of a singular logic gate
Truth Table of an AND Gate
What does De Morgan’s Theorem state
The complement of the product of two variables equals the sum of their complements
In depth description and explanation about De Morgan’s law
https://www.youtube.com/watch?v=ZyCzgqijpmM&list=PLTd6ceoshprcTJdg5AI6i2D2gZR5r8_Aw&index=3
What is a ‘Karnaugh Map’
• Special form of a truth table which enables easier
pattern recognition
• Pictorial method of simplifying Boolean expressions
• Good for circuit designs with up to 4 variables
Draw and simplify an OR gate using a K-Map
https://drive.google.com/file/d/1fDV76M88zM8cPG4cpZu6vrfy61-ktVoU/view?usp=sharing
Example of Simplification
https://drive.google.com/file/d/1BbUBaMwkc5cMjL2fhM7ckcVfpjbG1lG4/view?usp=sharing
Draw and Simplify this Truth Table and state the Logic Expression
• https://drive.google.com/file/d/10Ptg9SfWmjsN4naDYkGIw698LQJN6Yqh/view?usp=sharing
https://drive.google.com/file/d/1JfX_6HlF8WoJinImPB4K4_bawRJin1Us/view?usp=sharing
State the rules of Grouping for K-Maps
- A group must only contain 1’s, no 0’s
- A group can only be horizontal or vertical, not diagonal
- A group must contain 2^n 1’s (1, 2, 4, 8 etc.)
- Each group should be as large as possible
- Groups may overlap
- Every 1 must be in at least one group
- There should be as few groups as possible
What are Combinational and Sequential Circuits?
Combinational
• A circuit in which the output is dependent only on the
input values
Sequential
• A circuit in which the output depends on the input
values and the previous output
What is an example of a Combinational Circuit?
A Half or Full Adder
What are Half Adders used for?
Binary Addition
What are the two outputs of a Half Adder called?
Sum and Carry
What gates make up a single Half Adder?
- AND Gate
* XOR Gate
Draw a Half Adder (Not Simplified Version!)
https://drive.google.com/file/d/1PiykA_Qlb82eESrfzTZFAljYjF96Rjbz/view?usp=sharing
Draw a Truth Table for a Half Adder
https://drive.google.com/file/d/1mADTdCmGBkwsuL2Zl9Lpi1vViS0gULUk/view?usp=sharing
What is the purpose of a Full Adder?
A Full Adder adds together two binary digits, plus a carry-in digit to produce a sum and carry-out digit. It therefore has three inputs and two outputs.
What are the outputs of a Full Adder called?
Sum and Carry
What gates make up a Full Adder?
- 2 Half Adders
* OR Gate
Draw a Full Adder (Not Simplified Version!)
https://drive.google.com/file/d/1pU0BAO4bMGsotrK0fxKmNUvL1Vh7ZFTY/view?usp=sharing
Draw a Truth Table for a Full Adder
https://drive.google.com/file/d/1NGF_TfMlEDEGF7VPjxRJ6vPMVEzRO4z_/view?usp=sharing
What is an example of a Sequential Circuit?
- SR Flip Flop (Latch)
* JK Flip Flip (Latch)
What gates can be used to construct a SR Flip Flop (Latch)?
- 2 NOR Gates
* 2 NAND Gates
What are the two states that a SR Flip Flop (Latch) can be in?
- When Q is set to 1 and Q̅ is set to 0
* When Q is set to 0 and Q̅ is set to 1
Draw a SR Flip Flop (Latch) with NOR Gates
https://drive.google.com/file/d/1SVMSZ7wc59iAhLbM9QsQdjudV3uJG61r/view?usp=sharing
Draw the Truth Table for a SR Flip Flop (Latch) with NOR Gates
https://drive.google.com/file/d/1LGDXgf59yGxglC9mJfK_HmaRiD1ohjVW/view?usp=sharing
Draw a SR Flip Flop (Latch) with NAND Gates
https://drive.google.com/file/d/1__2dJvqt7fiBP9wFg5jQA80xCb5CkCPh
Draw a Truth Table for a SR Flip Flop (Latch) with NAND Gates
https://drive.google.com/file/d/1NkRVxMGTJxpagIo7WDE60yXt5cFOse_p
What gates can be used to construct a JK Flip Flop (Latch)?
NAND Gate Version: • 2 NAND Gates • A Clock (2 NAND Gates) NOR Gate Version: • 2 NOR Gates •A Clock (2 AND Gates)
Draw a JK Flip Flop (Latch) with NOR Gates
https://drive.google.com/file/d/16SdC0Swv03b45QI7QI80kQ6iq9JP9Nwu/view?usp=drivesdk
