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IAL Computing Cambridge > Chapter 18 Boolean Algebra and Logic Circuits > Flashcards

Chapter 18 Boolean Algebra and Logic Circuits Flashcards

1
Q

State the ‘Annulment’ Law for both AND/OR

A 
AND Version
• A ^ 0 = 0
• A . 0 = 0
OR Version
• A v 1 = 1
• A + 1 = 1
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2
Q

State the ‘Identity’ Law for both AND/OR

A 
AND Version
• A ^ 1 = A
• A . 1  = A
OR Version
• A v 0 = A
• A + 0 = A
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3
Q

State the ‘Idempotent’ Law for both AND/OR

A 
AND Version
• A ^ A = A
• A . A = A
OR Version
• A v A = A 
• A + A = A
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4
Q

State the ‘Complement’ Law for both AND/OR

A 
AND Version
• A ^ ¬A = 0
• A . ¬A = 0
OR Version
• A v ¬A = 1
• A + ¬A = 1
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5
Q

State the ‘Double Negation’ Law

A

¬(¬A) = A

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6
Q

State the ‘Associative’ Law for both AND/OR

A 
AND Version
• (A ^ B) ^ C = A ^ (B ^ C)
• (A . B) . C = A . (B . C)
OR Version
• (A v B) v C = A v (B v C)
• (A + B) + C = A + (B + C)
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7
Q

State the ‘Commutative’ Law for both AND/OR

A 
AND Version
• A ^ B = B ^ A
• A . B = B ^ A
OR Version
• A v B = B v A
• A + B = B + A
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8
Q

State the both version of the ‘Distributive’ Law

A 
First Version
• A ^ (B v C) = (A ^ B) v (A ^ C)
• A . (B + C) = (A . B) + (A . C)
Second Version
• A v (B ^ C) = (A v B) ^ (A v C)
• A + (B . C) = (A + B) . (A + C)
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9
Q

State the both version of the ‘Absorptive’ Law

A 
First Version
• A ^ (B v C) = A
• A . (B + C) = A
Second Version
• A v (B ^ C) = A
• A + (B . C) = A
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10
Q

State the both version of the ‘De Morgan’s’ Law

A 
First Version
• ¬(A ^ B) = ¬A v ¬B
• ¬(A . B) = ¬A + ¬B
Second Version
• ¬(A v B) = ¬A ^ ¬B
• ¬(A + B) = ¬A . ¬B
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11
Q

Youtube Video with logic circuit representation of all boolean algebra laws and Image of all Boolean Algebra Laws

A
  • YT vid: https://www.youtube.com/watch?v=EPJf4owqwdA

* Image: https://drive.google.com/file/d/1AERcZmNuuCFX6kuvxOqfS4I9dY8YbwnY/view?usp=sharing

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12
Q

What does ‘Boolean Addition’ correspond to in terms of a singular logic gate

A

Truth Table of an OR Gate

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13
Q

What does ‘Boolean Multiplication’ correspond to in terms of a singular logic gate

A

Truth Table of an AND Gate

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14
Q

What does De Morgan’s Theorem state

A

The complement of the product of two variables equals the sum of their complements

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15
Q

In depth description and explanation about De Morgan’s law

A

https://www.youtube.com/watch?v=ZyCzgqijpmM&list=PLTd6ceoshprcTJdg5AI6i2D2gZR5r8_Aw&index=3

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16
Q

What is a ‘Karnaugh Map’

A

• Special form of a truth table which enables easier
pattern recognition
• Pictorial method of simplifying Boolean expressions
• Good for circuit designs with up to 4 variables

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17
Q

Draw and simplify an OR gate using a K-Map

A

https://drive.google.com/file/d/1fDV76M88zM8cPG4cpZu6vrfy61-ktVoU/view?usp=sharing

18
Q

Example of Simplification

A

https://drive.google.com/file/d/1BbUBaMwkc5cMjL2fhM7ckcVfpjbG1lG4/view?usp=sharing

19
Q

Draw and Simplify this Truth Table and state the Logic Expression
• https://drive.google.com/file/d/10Ptg9SfWmjsN4naDYkGIw698LQJN6Yqh/view?usp=sharing

A

https://drive.google.com/file/d/1JfX_6HlF8WoJinImPB4K4_bawRJin1Us/view?usp=sharing

20
Q

State the rules of Grouping for K-Maps

A
  • A group must only contain 1’s, no 0’s
  • A group can only be horizontal or vertical, not diagonal
  • A group must contain 2^n 1’s (1, 2, 4, 8 etc.)
  • Each group should be as large as possible
  • Groups may overlap
  • Every 1 must be in at least one group
  • There should be as few groups as possible
21
Q

What are Combinational and Sequential Circuits?

A

Combinational
• A circuit in which the output is dependent only on the
input values
Sequential
• A circuit in which the output depends on the input
values and the previous output

22
Q

What is an example of a Combinational Circuit?

A

A Half or Full Adder

23
Q

What are Half Adders used for?

A

Binary Addition

24
Q

What are the two outputs of a Half Adder called?

A

Sum and Carry

25
Q

What gates make up a single Half Adder?

A
  • AND Gate

* XOR Gate

26
Q

Draw a Half Adder (Not Simplified Version!)

A

https://drive.google.com/file/d/1PiykA_Qlb82eESrfzTZFAljYjF96Rjbz/view?usp=sharing

27
Q

Draw a Truth Table for a Half Adder

A

https://drive.google.com/file/d/1mADTdCmGBkwsuL2Zl9Lpi1vViS0gULUk/view?usp=sharing

28
Q

What is the purpose of a Full Adder?

A

A Full Adder adds together two binary digits, plus a carry-in digit to produce a sum and carry-out digit. It therefore has three inputs and two outputs.

29
Q

What are the outputs of a Full Adder called?

A

Sum and Carry

30
Q

What gates make up a Full Adder?

A
  • 2 Half Adders

* OR Gate

31
Q

Draw a Full Adder (Not Simplified Version!)

A

https://drive.google.com/file/d/1pU0BAO4bMGsotrK0fxKmNUvL1Vh7ZFTY/view?usp=sharing

32
Q

Draw a Truth Table for a Full Adder

A

https://drive.google.com/file/d/1NGF_TfMlEDEGF7VPjxRJ6vPMVEzRO4z_/view?usp=sharing

33
Q

What is an example of a Sequential Circuit?

A
  • SR Flip Flop (Latch)

* JK Flip Flip (Latch)

34
Q

What gates can be used to construct a SR Flip Flop (Latch)?

A
  • 2 NOR Gates

* 2 NAND Gates

35
Q

What are the two states that a SR Flip Flop (Latch) can be in?

A
  • When Q is set to 1 and Q̅ is set to 0

* When Q is set to 0 and Q̅ is set to 1

36
Q

Draw a SR Flip Flop (Latch) with NOR Gates

A

https://drive.google.com/file/d/1SVMSZ7wc59iAhLbM9QsQdjudV3uJG61r/view?usp=sharing

37
Q

Draw the Truth Table for a SR Flip Flop (Latch) with NOR Gates

A

https://drive.google.com/file/d/1LGDXgf59yGxglC9mJfK_HmaRiD1ohjVW/view?usp=sharing

38
Q

Draw a SR Flip Flop (Latch) with NAND Gates

A

https://drive.google.com/file/d/1__2dJvqt7fiBP9wFg5jQA80xCb5CkCPh

39
Q

Draw a Truth Table for a SR Flip Flop (Latch) with NAND Gates

A

https://drive.google.com/file/d/1NkRVxMGTJxpagIo7WDE60yXt5cFOse_p

40
Q

What gates can be used to construct a JK Flip Flop (Latch)?

A 
NAND Gate Version:
• 2 NAND Gates 
• A Clock (2 NAND Gates)
NOR Gate Version:
• 2 NOR Gates
•A Clock (2 AND Gates)
41
Q

Draw a JK Flip Flop (Latch) with NOR Gates

A

https://drive.google.com/file/d/16SdC0Swv03b45QI7QI80kQ6iq9JP9Nwu/view?usp=drivesdk

IAL Computing Cambridge (4 decks)

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