Chapter 15 Flashcards
"Hardware and Virtual Machines"
RISC (reduced instruction set computer)
assembly code is broken into a number of single cycle instructions
- fewer, simpler instructions
- few instruction formats
- fewer addressing modes
- single-cycle instructions
- fixed-length instructions
- easier to pipleine
- fewer addressing modes
- many registers (general purpose)
- hardwired CU
- more emphasis on software
CISC (complex instruction set computer)
aims to carry out a given task in as few lines of code possible
- more complex instructions
- many instruction formats
- multicycle instructions
- variable length instructions
- more addressing modes
- fewer registers (most processing is done in memory)
- microprogrammed control unit
- pipelining is more difficult (variable length)
- emphasis on hardware
hardwired control unit
uses logic circuits, e.g. flip flops
microprogrammed control unit
uses programs, code will compile, run and generate output
what is pipelining?
- allows several instructions to be processed simultaneously
- therefore increasing the number of instructions completed per unit time
- each stage of instruction is completed during one clock cycle
- when the first stage of an instruction is completed the first stage of the next instruction can start executing
- another instruction can start executing before the previous one is finished
- processing several instructions can be done simultaneously
pipelining during the fetch-execute cycle in RISC processors
- Instructions are divided into subtasks / 5 stages
- … Instruction fetch / IF, Instruction decode / ID, operand fetch / OF, opcode/instruction execute IE, result store / write back result / WB
- Each subtask is completed during one clock cycle
- No two instructions can execute their same stage at the same clock cycle
- The second instruction begins in the second clock cycle, while the first instruction has moved on to its second subtask.
- The third instruction begins in the third clock cycle while the first and second instructions move on to their second and third subtasks, respectively, etc.
interrupt handling with pipelining
when an interrupt occurs:
option 1: erase the pipeline
option 2: construct individual units in processor with individual program counters. this allows current data to be stored for all instructions in pipeline while interrupt is handled.
SISD
single instruction single data
processor executes one set of instructions on one data set
only one processor
commonly used among early personal computers
no ability for parallel processing
SIMD
single instruction multiple data
- many processors execute the same instruction using different data sets
- has several ALUs
- each ALU executes the same instruction on different data sets at the same time
used in sound sampling
MISD
multiple instruction single data
several processors
* many processors execute different instructions on the same data set at the same time
not commercially used
MIMD
multiple instruction multiple data
* several processors
* many processors executing different instructions on different data sets
used in most modern personal systems
uses parallel processing
massively parallel computers
- large number of processors, usually within the same computer
- working collaboratively and simultaneously on the same program
- communicating via message interface
- network infrastructure
hardware issue in massively parallel computers and cluster computing (they are not the same though)
- processors need to be able to communicate
- so that processed data can be transferred
- from one processor to another
- so it’s a very challenging topology
software issue in massively parallel computers
appropriate programming language should be used
which allows data to be processed by multiple processors simultaneously
cluster computing
large number of computers/PCs are linked/networked together.
each computer’s processor forms part of a larger pseudo-parallel system, acting as a supercomputer.
