Chapter 12: I/O Systems (Ch 12 Silberschatz) Flashcards
Port: (I/O Systems)
port: A communication address; a system may have one IP address for network connections but many ports, each for a separate communication. In computer I/O, a connection point for devices to attach to computers. In software development, to move code from its current platform to another platform (e.g., between operating systems or hardware systems). In the Mach OS, a mailbox for communication.
Phy: (I/O Systems)
PHY: The physical hardware component that connects to a network (implements layer 1 in the OSI model).
Bus: (I/O Systems)
bus: A communication system; e.g., within a computer, a bus connects various components, such as the CPU and I/O devices, allowing them to transfer data and commands.
Daisy Chain: (I/O Systems)
daisy chain: In computer I/O, a connection method involving connecting devices to each other in a string (device A to B, B to C, C to D, etc.).
Pcie Bus: (I/O Systems)
PCIe bus: A common computer I/O bus connecting the CPU to I/O devices.
Expansion Bus: (I/O Systems)
expansion bus: A computer bus for connecting slow devices like keyboards.
Serial-Attached Scsi (Sas): (I/O Systems)
serial-attached SCSI (SAS): A common type of I/O bus.
Sas: (I/O Systems)
SAS: A common type of I/O bus.
Controller: (I/O Systems)
controller: A special processor that manages I/O devices.
Fibre Channel (Fc): (I/O Systems)
fibre channel (FC): A type of storage I/O bus used in data centers to connect computers to storage arrays. A storage-attachment network.
Host Bus Adapter (Hba): (I/O Systems)
host bus adapter (HBA): A device controller installed in a host bus port to allow connection of one or more devices to the host.
Memory-Mapped I/O: (I/O Systems)
memory-mapped I/O: A device I/O method in which device-control registers are mapped into the address space of the processor.
Data-In Register: (I/O Systems)
data-in register: A device I/O register where data is placed to be sent to the device.
Data-Out Register: (I/O Systems)
data-out register: A device I/O register where data is placed by the device to be read by the computer.
Status Register: (I/O Systems)
status register: A device I/O register in which status is indicated.
Control Register: (I/O Systems)
control register: A device I/O register where commands are placed by the computer.
Busy Waiting: (I/O Systems)
busy waiting: A practice that allows a thread or process to use CPU time continuously while waiting for something. An I/O loop in which an I/O thread continuously reads status information while waiting for I/O to complete.
Polling: (I/O Systems)
polling: An I/O loop in which an I/O thread continuously reads status information waiting for I/O to complete.
Interrupt: (I/O Systems)
interrupt: A hardware mechanism that enables a device to notify the CPU that it needs attention.
Interrupt-Request Line: (I/O Systems)
interrupt-request line: The hardware connection to the CPU on which interrupts are signaled.
Interrupt-Handler Routine: (I/O Systems)
interrupt-handler routine: An operating system routine that is called when an interrupt signal is received.
Interrupt-Controller Hardware: (I/O Systems)
interrupt-controller hardware: Computer hardware components for interrupt management.
Nonmaskable Interrupt: (I/O Systems)
nonmaskable interrupt: An interrupt that cannot be delayed or blocked (such as an unrecoverable memory error)
Maskable: (I/O Systems)
maskable: Describes an interrupt that can be delayed or blocked (such as when the kernel is in a critical section).
Address Space Layout Randomization (Aslr): (I/O Systems)
address space layout randomization (ASLR): An operating system technique to avoid code-injection attacks that place memory objects like the stack and heap at unpredictable locations.
Interrupt Vector: (I/O Systems)
interrupt vector: An operating-system data structure indexed by interrupt address and pointing to the interrupt handlers. A kernel memory data structure that holds the addresses of the interrupt service routines for the various devices.
Interrupt Chaining: (I/O Systems)
interrupt chaining: A mechanism by which each element in an interrupt vector points to the head of a list of interrupt handlers, which are called individually until one is found to service the interrupt request.
Interrupt Priority Level: (I/O Systems)
interrupt priority level: Prioritization of interrupts to indicate handling order.
Exception: (I/O Systems)
exception: A software-generated interrupt caused either by an error (such as division by zero or invalid memory access) or by a specific request from a user program than an operating-system service be performed.
First-Level Interrupt Handler: (I/O Systems)
first-level interrupt handler: In some operating systems, an interrupt handler responsible for reception and queuing of interrupts; the interrupts are actually handled at another level (by the second-level handler).
Second-Level Interrupt Handler: (I/O Systems)
second-level interrupt handler: In some operating systems, the interrupt handler that actually handles interrupts; reception and queueing of interrupts are handled at another level (by the first-level handler).
Software Interrupt: (I/O Systems)
software interrupt: A software-generated interrupt; also called a trap. The interrupt can be caused either by an error (e.g., division by zero or invalid memory access) or by a specific request from a user program that an operating-system service be performed.
Trap: (I/O Systems)
trap: A software interrupt. The interrupt can be caused either by an error (e.g., division by zero or invalid memory access) or by a specific request from a user program that an operating-system service be performed.
Programmed I/O (Pio): (I/O Systems)
programmed I/O (PIO): A method of transferring data between a CPU and a peripheral device in which data are transferred one byte at a time.
Direct Memory Access (Dma): (I/O Systems)
direct memory access (DMA): A resource-conserving and performance-improving operation for device controllers allowing devices to transfer large amounts of data directly to and from main memory.
Scatter-Gather: (I/O Systems)
scatter-gather: An I/O method in which multiple sources or destinations of I/O are specified in one command structure.
Double Buffering: (I/O Systems)
double buffering: The copying of data twice (e.g., from a device to the kernel and then from the kernel to a process’s address space), or the use of two buffers to decouple producers and consumers.
Cycle Stealing: (I/O Systems)
cycle stealing: The act of a device, such as a DMA controller, using the bus and preventing the CPU from using it temporarily.
Direct Virtual Memory Access (Dvma): (I/O Systems)
direct virtual memory access (DVMA): DMA that uses virtual addresses rather than physical memory addresses as transfer sources and destinations.
The device drivers present a uniform device-access interface to the
I/O subsystem, much as system calls provide a standard interface between the application and the operating system.
