Chapter 12: I/O Systems (Ch 12 Silberschatz)

Question 1

Port: (I/O Systems)

Answer 1

port: A communication address; a system may have one IP address for network connections but many ports, each for a separate communication. In computer I/O, a connection point for devices to attach to computers. In software development, to move code from its current platform to another platform (e.g., between operating systems or hardware systems). In the Mach OS, a mailbox for communication.

Question 2

Phy: (I/O Systems)

Answer 2

PHY: The physical hardware component that connects to a network (implements layer 1 in the OSI model).

Question 3

Bus: (I/O Systems)

Answer 3

bus: A communication system; e.g., within a computer, a bus connects various components, such as the CPU and I/O devices, allowing them to transfer data and commands.

Question 4

Daisy Chain: (I/O Systems)

Answer 4

daisy chain: In computer I/O, a connection method involving connecting devices to each other in a string (device A to B, B to C, C to D, etc.).

Question 5

Pcie Bus: (I/O Systems)

Answer 5

PCIe bus: A common computer I/O bus connecting the CPU to I/O devices.

Question 6

Expansion Bus: (I/O Systems)

Answer 6

expansion bus: A computer bus for connecting slow devices like keyboards.

Question 7

Serial-Attached Scsi (Sas): (I/O Systems)

Answer 7

serial-attached SCSI (SAS): A common type of I/O bus.

Question 8

Sas: (I/O Systems)

Answer 8

SAS: A common type of I/O bus.

Question 9

Controller: (I/O Systems)

Answer 9

controller: A special processor that manages I/O devices.

Question 10

Fibre Channel (Fc): (I/O Systems)

Answer 10

fibre channel (FC): A type of storage I/O bus used in data centers to connect computers to storage arrays. A storage-attachment network.

Question 11

Host Bus Adapter (Hba): (I/O Systems)

Answer 11

host bus adapter (HBA): A device controller installed in a host bus port to allow connection of one or more devices to the host.

Question 12

Memory-Mapped I/O: (I/O Systems)

Answer 12

memory-mapped I/O: A device I/O method in which device-control registers are mapped into the address space of the processor.

Question 13

Data-In Register: (I/O Systems)

Answer 13

data-in register: A device I/O register where data is placed to be sent to the device.

Question 14

Data-Out Register: (I/O Systems)

Answer 14

data-out register: A device I/O register where data is placed by the device to be read by the computer.

Question 15

Status Register: (I/O Systems)

Answer 15

status register: A device I/O register in which status is indicated.

Question 16

Control Register: (I/O Systems)

Answer 16

control register: A device I/O register where commands are placed by the computer.

Question 17

Busy Waiting: (I/O Systems)

Answer 17

busy waiting: A practice that allows a thread or process to use CPU time continuously while waiting for something. An I/O loop in which an I/O thread continuously reads status information while waiting for I/O to complete.

Question 18

Polling: (I/O Systems)

Answer 18

polling: An I/O loop in which an I/O thread continuously reads status information waiting for I/O to complete.

Question 19

Interrupt: (I/O Systems)

Answer 19

interrupt: A hardware mechanism that enables a device to notify the CPU that it needs attention.

Question 20

Interrupt-Request Line: (I/O Systems)

Answer 20

interrupt-request line: The hardware connection to the CPU on which interrupts are signaled.

Question 21

Interrupt-Handler Routine: (I/O Systems)

Answer 21

interrupt-handler routine: An operating system routine that is called when an interrupt signal is received.

Question 22

Interrupt-Controller Hardware: (I/O Systems)

Answer 22

interrupt-controller hardware: Computer hardware components for interrupt management.

Question 23

Nonmaskable Interrupt: (I/O Systems)

Answer 23

nonmaskable interrupt: An interrupt that cannot be delayed or blocked (such as an unrecoverable memory error)

Question 24

Maskable: (I/O Systems)

Answer 24

maskable: Describes an interrupt that can be delayed or blocked (such as when the kernel is in a critical section).

Question 25

Address Space Layout Randomization (Aslr): (I/O Systems)

Answer 25

address space layout randomization (ASLR): An operating system technique to avoid code-injection attacks that place memory objects like the stack and heap at unpredictable locations.

Question 26

Interrupt Vector: (I/O Systems)

Answer 26

interrupt vector: An operating-system data structure indexed by interrupt address and pointing to the interrupt handlers. A kernel memory data structure that holds the addresses of the interrupt service routines for the various devices.

Question 27

Interrupt Chaining: (I/O Systems)

Answer 27

interrupt chaining: A mechanism by which each element in an interrupt vector points to the head of a list of interrupt handlers, which are called individually until one is found to service the interrupt request.

Question 28

Interrupt Priority Level: (I/O Systems)

Answer 28

interrupt priority level: Prioritization of interrupts to indicate handling order.

Question 29

Exception: (I/O Systems)

Answer 29

exception: A software-generated interrupt caused either by an error (such as division by zero or invalid memory access) or by a specific request from a user program than an operating-system service be performed.

Question 30

First-Level Interrupt Handler: (I/O Systems)

Answer 30

first-level interrupt handler: In some operating systems, an interrupt handler responsible for reception and queuing of interrupts; the interrupts are actually handled at another level (by the second-level handler).

Question 31

Second-Level Interrupt Handler: (I/O Systems)

Answer 31

second-level interrupt handler: In some operating systems, the interrupt handler that actually handles interrupts; reception and queueing of interrupts are handled at another level (by the first-level handler).

Question 32

Software Interrupt: (I/O Systems)

Answer 32

software interrupt: A software-generated interrupt; also called a trap. The interrupt can be caused either by an error (e.g., division by zero or invalid memory access) or by a specific request from a user program that an operating-system service be performed.

Question 33

Trap: (I/O Systems)

Answer 33

trap: A software interrupt. The interrupt can be caused either by an error (e.g., division by zero or invalid memory access) or by a specific request from a user program that an operating-system service be performed.

Question 34

Programmed I/O (Pio): (I/O Systems)

Answer 34

programmed I/O (PIO): A method of transferring data between a CPU and a peripheral device in which data are transferred one byte at a time.

Question 35

Direct Memory Access (Dma): (I/O Systems)

Answer 35

direct memory access (DMA): A resource-conserving and performance-improving operation for device controllers allowing devices to transfer large amounts of data directly to and from main memory.

Question 36

Scatter-Gather: (I/O Systems)

Answer 36

scatter-gather: An I/O method in which multiple sources or destinations of I/O are specified in one command structure.

Question 37

Double Buffering: (I/O Systems)

Answer 37

double buffering: The copying of data twice (e.g., from a device to the kernel and then from the kernel to a process's address space), or the use of two buffers to decouple producers and consumers.

Question 38

Cycle Stealing: (I/O Systems)

Answer 38

cycle stealing: The act of a device, such as a DMA controller, using the bus and preventing the CPU from using it temporarily.

Question 39

Direct Virtual Memory Access (Dvma): (I/O Systems)

Answer 39

direct virtual memory access (DVMA): DMA that uses virtual addresses rather than physical memory addresses as transfer sources and destinations.

Question 40

The device drivers present a uniform device-access interface to the

Answer 40

I/O subsystem, much as system calls provide a standard interface between the application and the operating system.