Chapter 1 Flashcards
The Control Unit
Controls & coordinates the activities of the CPU and other parts of the computer. It controls the F-D-E cycle by sending signals through the control bus.
The Clock
A vibrating quartz crystal the coordinates instruction executions.
The Arithmetic & Logic Unit
Performs arithmetic and logic operations on the data such as: add, subtract, multiply and divide. It can also perform shift operations and the Boolean logic operations AND, OR, NOT & XOR.
Register
A memory location within the processor that stores specific data and operate at a very high speed.
Cache
A small amount of memory in the CPU that can be accessed even faster than RAM.
The Control Bus
A bi-directional bus: signals are sent both to and from the processor. Data and Address buses connect all computer components together and control lines are needed to ensure all components use the Data and Address busses fairly.
Control Lines include:
- Bus Request: A device is requesting use of a Data bus
- Bus Grant: The CPU has granted access to a Data bus
- Memory Write: Let the data on the Data bus write to a memory location
- Memory Read: Let data from address location be put on the Data bus
- Interrupt Request: A component is requesting access to the CPU
- Clock: Synchronises the F-D-E cycle
The Data Bus
Provides a bi-directional path for moving data and instructions between components.
The Address Bus
Uni-directional bus, that transmits the location of stored information. Allows the CPU to send the address to RAM.
No. of typical general purpose registers
16
Accumulator (Acc)
Used by the ALU to perform arithmetic, logic and shift operations.
Program Counter (PC)
Keeps track of thee address of the next program instruction. Sends the address to the memory address register.
Memory Address Register (MAR)
Receives the address of the next instruction from the program counter and sends it to the memory.
Memory Data Register (MDR)
Receives the instruction from the memory. Copies the instruction to the current instruction register.
Current Instruction Register (CIR)
Receives the instruction form the memory data register before it is decoded by the control unit.
Fetch (FDE Cycle)
- The address of the next instruction from the program counter to the memory address register
- The instruction held at that address is copied to the memory data register. Simultaneously, the content of the PC is incremented so that it holds that address of the next instruction.
- The contents of the MDR are copied to the current instruction register (CIR)
Decode (FDE Cycle)
- The instruction held in the CIR is decoded. The instruction is split into opcode and operand and the opcode is used to determine the type of instruction and what hardware to use to execute it. The operand holds either:
- the address of the data to be used with operation, which is then copied to the MAR
- the actual data to be operated on, which will be copied to the MDR
-the data to be operated on may be passed to the ALU/Acc
Execute (FDE Cycle)
- The appropriate instruction/opcode is carried out on the operand.
Instruction word
Contains an opcode and an operand
Factors of processor performance
- Clock Speed
- Number of cores
- Amount of RAM
- Amount and type of Cache
- Size of words computer is designed to use
-Pipelining
-Amount & size of general purpose registers
Overclocking
When you make the clock run faster than its
design parameters; this causes more FDE cycles to occur per
second, but the increased electrical signals cause more heat,
increasing the risk of damage. Precautions such as additional
heat sinks and fans to dissipate
the heat are required.
