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Question 1

CISC processor

Answer 1

Uses many instruction formats
 Uses variable length instructions
 Makes use of different addressing modes
 Uses few registers
 Has a large instruction set
 Requires complex circuits(emphasizes on hardware)

Question 2

RISC processor

Answer 2

Uses simple instructions
 Uses fixed length instructions
 Instructions only require one clock cycle
 Uses many registers
 Makes use of pipelining
 Hardwired CU
(emphasizes on software)

Question 3

Pipelining

Answer 3

allows several instructions to be processed simultaneously without having to wait for previous instructions to finish, this development is a result from RISC architecture

Question 4

Identify two differences between RISC and CISC processors

Answer 4

RISC has fewer instructions // CISC has more instructions
 RISC has many registers // CISC has few registers
 RISC’s instructions are simpler // CISC’s instructions are more complex
 RISC has a few instruction formats / CISC has many instruction formats
 RISC usually uses single-cycle instructions// CISC uses multi-cycle instructions

Question 5

Parallel processing

Answer 5

operation which allows a process to be split up and for each part to be executed by a different processor at the same time.

Question 6

SIMD

Answer 6

many processors execute the same instruction using different data sets. they are all doing the same calculations but on different data at the same time. parallel computers with multiple processors.takes advantage of pipeling

Question 7

MISD

Answer 7

many processors (using different instructions) use the same data set. uses pipelining. parallel computers with multiple processors

Question 8

MIMD

Answer 8

many processors (using different instructions) using different data sets. many processors that operate independently

Question 9

SISD

Answer 9

a single processor that can handle a single instruction and which also uses one data source at a time. each task is processed in a sequential order. it does not allow for parallel processing since it has a single processor. uses pipelining.

Question 10

cluster

Answer 10

a number of computers (containing SIMD processors) networked together.

Question 11

Massively parallel computers

Answer 11

the linking together of several computers effectively forming one machine with thousands of processors

Question 12

Outline the characteristics of massively parallel computers

Answer 12

A large number of computer processors / separate computers
connected together
MP2 … simultaneously performing a set of coordinated computations //
collaborative processing
MP3 network infrastructure
MP4 communicate using a message interface

Question 13

Describe the use of pipelining in Reduced Instruction Set Computers (RISC)

Answer 13

Pipelining allows several instructions to be processed simultaneously
/ concurrently.
MP2 … therefore, increasing the CPU instruction throughput / the number
of instructions completed per unit of time.
MP3 Each instruction stage / subtask is completed during one clock cycle

Question 14

Describe the process of pipelining during the fetch-execute cycle in RISC processors.

Answer 14

Instructions are divided into subtasks / 5 stages
* … Instruction fetch / IF, Instruction decode / ID, operand fetch / OF, opcode/instruction execute IE, result store / write
back result / WB
* Each subtask is completed during one clock cycle
* No two instructions can execute their same stage at the same clock cycle

Question 15

State the purpose of a flip-flop.

Answer 15

To store a binary digit

Question 16

what are the five stages of execution in pipelining

Answer 16

1. instruction fetch cycle (IF)
2. instruction decode cycle (ID)
   3.operand fetch cycle (OF)
3. instruction execution cycle (IE)
4. writeback result process (WB)

In pipelining, each stage of instruction execution takes one clock cycle to complete. This requires processors with multiple registers to store each stage of the pipeline

Question 17

interrupt handling in pipelining

Answer 17

The usual way to deal with this is to discard all instructions in the pipeline except for the last instruction in the write-back (WB) stage. The interrupt handler routine can then be applied to this remaining instruction and, once serviced, the processor can restart with the next instruction in the sequence. Alternatively, although much less common, the contents of the five stages can be stored in registers. This allows all current data to be stored, allowing the processor to be restored to its previous status once the interrupt has been serviced.

Question 18

parallel processing

Answer 18

operation which allows a process to be split up and for each part to be executed by a different processor at the same time