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COSC 3360: Fundamentals of Operating Systems > Ch 1: Computer System Overview > Flashcards

Ch 1: Computer System Overview Flashcards

1
Q

Define Processor.

A

Controls the operation of the computer (CPU), performs data processing; read from main memory

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2
Q

Define Main Memory.

A

Stores data and information and is usually volatile. Its contents are lost when the computer is shut down (except for disk memory).

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3
Q

Define I/O Modules.

A

Moves the data between the computer and external environments like storage (hard drive), communications equipment (mouse/keyboard), and terminals

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4
Q

Define System Bus.

A

Provides communication among processors, main memory, and I/O modules.

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5
Q

Define PC.

A

Stands for program counter. It has the address of the next instruction to be executed from main memory.

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6
Q

Define IR.

A

Stands for instruction register. It holds the instruction currently being executed or decoded. Each instruction that is to be executed is loaded into the instruction register.

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7
Q

Define MAR.

A

Stands for memory address register. It either stores the memory address from which data will be fetched, or the address to which data will be sent and stored via System Bus.

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8
Q

Define MBR.

A

Stands for memory buffer register. It stores the data being transferred to and from the immediate access storage. It contains a copy of the value in the memory location specified.

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9
Q

Define I/O AR.

A

Stands for input/output address register. It provides the transfer of information from inputs to the central computer, or from it to the output equipment.

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10
Q

Define I/O BR.

A

Stands for input/output buffer register. It contains data to be read from an I/O buffer or to be written into one.

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11
Q

What is the first step of program execution?

A

The processors reads instruction from the main memory.

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12
Q

What is the second step of program execution?

A

The processors executes each instruction

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13
Q

Define Processor-Memory in IR.

A

Data may be transferred from processor to memory or from memory to processor.

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14
Q

Define Processor-I/O.

A

Data may be transferred to or from a peripheral device by transferring between the processor and an I/O module.

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15
Q

Define Data Processing in IR.

A

The processor may perform some arithmetic or logic operation on data.

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16
Q

Define Control in IR.

A

An instruction may specify that the sequence of execution be altered.

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17
Q

What is the formula to find the number of of instructions?

A

2^(size of opcode in bits)

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18
Q

What is the formula to find the number of positions?

A

2^(# of bits of address)

19
Q

What is the formula to find the size of the positions?

A

16 bits = 2 bytes

20
Q

What is the formula to find the size of memory (bytes)?

A

of positions * size of position

21
Q

What is the purpose of Interrupts?

A

They are provided to improve processor utilization. They interrupt the normal sequencing of the processor.
a) most I/O devices are slower than the processor
b) processor must pause to wait for device
c) wasteful use of the processor

22
Q

Describe the steps of Interrupt Processing.

A
  1. The device issues an interrupt signal to the processor.
  2. The processor finishes execution of the current instruction before responding to the interrupt.
  3. The processor tests for a pending interrupt request. If there is, then it gives a signal to the device that issued the interrupt. The device removes the interrupt signal.
  4. The processor then needs to transfer control to the interrupt routine. It saves the info to resume the current program where it was interrupted.
  5. The processor loads the PC.
  6. The interrupt handler will save the contents of all register on the stack.
  7. The interrupt handler processes the interrupt by examining status info.
  8. The saved register values are retrieved from the stack and restored.
  9. Restore the PSW and PC values from the stack.
23
Q

What are the two approaches if there are multiple interrupts?

A
  1. Disable interrupts while an interrupt is being processed. The processor will ignore any new interrupt request signal.
  2. Define priorities for interrupts and allow an interrupt of higher priority to cause a lower-priority interrupt handler to be interrupted.
24
Q

What are the major constraints in memory?

A

Amount, speed, and expense. Memory must be able to keep up with the processor. The cost of memory must be reasonable in relationship to the other components.

25
Q

Give the Memory Hierarchy (top to bottom).

A

a. Decreasing cost per bit
b. Increasing capacity
c. Increasing access time
d. Decreasing frequency of access to the memory by the processor.

26
Q

Define Hit Ratio.

A

H is defined as the fraction of all memory accesses that are found in the faster memory (e.g the cache).

27
Q

Describe what the Average Access Time is.

A

The access time pertains to devices such as memory, hard drive, etc. It is the time from the start of one storage device access to the time when the next access can be started. The lower the time, the better the computer should perform. (e.g. ordering pizza and it being delivered)

28
Q

What is the formula to find the Average Access Time?

A

Avg. Access Time = T1 * Hit Ratio + (T2 + T1) * Miss Ratio

29
Q

What is the formula to find the Miss Ratio?

A

Miss Ratio = 1 - Hit Ratio

30
Q

Define the Principle of Locality.

A

The validity of the condition. It is the tendency of a processor to access the same set of memory locations repetitively over a short period of time.

31
Q

Describe what the Principle of Locality does.

A

It accesses the same set of memory locations repetitively over a short period of time. Memory references by the processor tend to cluster, therefore the data is organized so that the percentage of accesses to each successively lower level is substantially less than that of the level above. This can be applied across more than two levels of memory.

32
Q

Define Secondary Memory.

A

External, nonvolatile. Used to store program and data files.

33
Q

Define Cache Memory.

A

Interacts with other memory management hardware. The processors must access memory at least once per instruction cycle. Exploit the principle of locality with a small, fast memory.

34
Q

What is the purpose of Cache Memory?

A

It is intended to provide memory access time approaching that of the fastest memories available and at the same time support a large memory size that has the price of less expensive types of semiconductor memories.

35
Q

How does Cache Memory work?

A
  1. The cache contains a copy of a portion of main memory.
  2. The processor attempts to read a byte/word of memory and a check is made to determine if the byte/word is in the cache.
  3. If it is in the cache, then the byte/word is delivered to the processor.
  4. If not, then a block of main memory is read into the cache then step 3 occurs.
36
Q

What are the two constraints of the Mapping Function?

A

This determines which cache location the block will occupy.
1. When one block is read in, another may have to be replaced.
2. The more flexible the mapping function, the more complex is the circuitry required to search the cache.

37
Q

How is the LRU (Least Recently Used) Algorithm used?

A

It replaces a block that has been in the cache the longest with no references to it. It chooses which block to replace when a new block is to be loaded into the cache.

38
Q

Define the Write Policy.

A

It dictates when the memory write operation takes place. It minimizes write operations and leaves the main memory in an obsolete state.

39
Q

When can the write policy occur?

A

It can occur every time the block is updated/replaced.

40
Q

What are the drawbacks of Interrupt-Driven I/O?

A
  1. The transfer rate is limited by the speed.
  2. A number of instructions must be executed for each I/O transfer.
41
Q

Define Direct Memory Access.

A

Transfers the entire block of data directly to and from memory without going through the processor.

42
Q

Define Symmetric Multiprocessors (SMP).

A
  1. There are 2 or more similar processors of comparable capability.
  2. These processors share the same main memory and I/O facilities and are interconnected by a bus.
  3. All processors share access to I/O devices.
  4. All processors can perform the same functions (symmetric).
  5. The system is controlled by an integrated operating system that provides interaction between processors and the job, task, file, etc.
43
Q

What are the advantages of SMP (Symmetric Multiprocessors)?

A

Performance, Scaling, Availability, and Incremental Growth

COSC 3360: Fundamentals of Operating Systems (3 decks)

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