Caches Flashcards
Ideal memory properties
- large
- fast
- nonvolatile
- cheap
Types of cache misses
- Compulsory: data was never in the cache before
- Capacity: can’t fit all data in the cache
- Conflict: there is enough space, but structure doesn’t allow it to be used; collision, interference
Write and Replacement Policies
Cache hit
Cache miss
Cache Hit:
=> Write-through: main memory is always up to date, writes may be slow
=> Write-back: Data is written only to the cache, main memory is temporarily inconsistent
Cache Miss:
=>Write-allocate: To-be-written data item is read from main memory into the cache, write performed afterwards according to the write policy
=> Write-to-memory: Modification is performed only in main memory
Fully associative cache
- cache lines with fixed length
- data identified by tag-field
- memory access: searching all tags for address tag
Direct mapped cache
- cache lines with fixed length
- mapping from address to cache lines
- data identified by tag field
Cache design parameters
- size and set size
- line length
- write policy
- replacement policy
- using virtual or physical addresses for tagging/indexing
Ambiguity Problem
Identical virtual addresses point to different physical addresses at different points in time
Alias Problem
Different virtual addresses point to the same physical memory location
What is a memory hierarchy and how does it provide fast access and large capacity?
- Trade-off between speed and capacity when manufacturing
- In a memory hierarchy multiple levels of gradually faster types of physical memory are installed in front of each other, with the fastest and smallest memory being closest.
- The goal is to create an illusion of both fast and large memory
- Migrate data from slower to faster memory
Temporal vs spatial locality (definitions)
Temporal: data that have been accessed recently are likely to be accessed again
Spatial: Memory cells that are accessed within a short period of time are close together
Cache memory is divided into cache blocks. Why is it necessary?
- Each cache is divided into sets of cache lines
- Each set is used to cache specific parts of the main memory
- Size of cache block is determined by maximal data that can be transferred between cache and the lower memory level
Write-through vs write-back
Write-through: any update to a given memory location isn’t only applied to the cache, but also to main memory.
=> Main memory content is always up-to-date
Write-back: only cache is updated when data is modified. only when data is evicted from the cache, it is written back to the main memory.
How can we handle writes if the data is not in the cache?
Write-allocate: Data is first brought into the cache, then either write-through or write-back
Write-to-memory: Data is directly written to the main memory, without caching it first
What problems can arise with virtually-indexed virtually-tagged caches?
- Ambiguity: Same virtual address but different address spaces and therefore different physical addresses and values
=> invalidate cache on context switch - Aliasing: Different virtual addresses, same address space, same physical location, results in cache incoherence.
=> disallow mapping both addresses at the same time or disallow caching for shared segments
To what degree do virtually-indexed physically-tagged caches solve these issues?
+Ambiguity: tags are different for processes
- Aliasing: two virtual addresses can still result in different cache sets being used
