Cache

Question 1

A cache memory also called
L1 cache, L2 cache, and L3 cache,
which are located between the CPU register file
and main memory

Answer 1

Answer:

SRAM (Static Random Access Memory)

Question 2

How many unique addresses can be created with a computer system that has 12-bit memory address.

Answer 2

Answer: 4 Kilobytes

Consider a computer system where each memory address has m bits that form M = 2^m unique addresses.

Solution:
M = 2^m
M = 2^12 = (2^10 * 2^2) = (1024 x 4) = 4096

or
M = 4 Kilobytes

Question 3

For a system which uses a 16-bit address for each byte, a memory cache has 8 cache sets, with each set having 4 lines and each line containing a buffer of 16 bytes.

What is the capacity of this cache?

Answer 3

Answer: 512 bytes

C = capacity
S = number of Sets = [8 sets]
E = number of lines = [4 lines per set]
B = Block size (bytes) = [16 bytes]

C = S x E x B
C = 8 x 4 x 16 
C = 512 bytes

handling units
sets x (line/set) x (bytes/line)
sets and lines get canceled

Question 4

For a system which uses a 16-bit address for each byte, a memory cache has 8 cache sets, with each set having 4 lines and each line containing a buffer of 16 bytes.

How are many bits from a memory address used are used as the tag for cache entries?

Answer 4

Answer: 9 bits

m-bit address = [16-bit] 
S= 2^s => 8 = 2 ^s => s = 3
B = 2^b => 16 = 2^b => b = 4
E = 4 [not relevant in this question] 
t = tag (in bits) 

t = m - (s+b)
t = 16 - (3+4)
t = 16 - 7 
t = 9 bits

Question 5

For a system which uses a 16-bit address for each byte, a memory cache has 8 cache sets, with each set having 4 lines and each line containing a buffer of 16 bytes.

Given the memory address 0x4A21, which cache set might contain the data stored at that address?

Answer 5

Answer: cache set 2

S = Sets, B = Block Size, t = tag, E = lines.

m-bit address [16-bit]
S = 8 = 2^3, s = 3
B = 16 = 2 ^4, b = 4

0x4A21
010010100 010 0001

tag = 010010100
set index = 010 = 2
byte offset = 0001

Question 6

What is the 4-tuple cache organization

Answer 6

Answer: {S, E, B, m}

M = 2^m unique address
Cache is organized as an array of S = 2^s sets.
Each set consists of E cache lines.
Each line consists of a data block of B = 2^b bytes, a valid bit and a tag bit, t = m - (b+s).

Question 7

What are 3 classifications of caching based on the number of lines per set

Answer 7

Answer:

1. Direct-mapped cache - E = 1, which means there’s one line per set
2. Set associative cache - a cache with 1 < E < C/B aka E-way set associative cache
3. Fully associative cache - consists of a single set E = C/B. There are no set index bits in the address.

Question 8

Describe the impact of cache size

Answer 8

Answer:
On the one hand, a larger cache will tend to increase the hit rate. On the other hand, it is always harder to make large memories run faster. As a result, larger caches tend to increase the hit time. This explains why an L1 cache is smaller than an L2 cache, and an L2 cache is smaller than an L3 cache.

Question 9

What is a cache (“pronounced as cash”)?

Answer 9

Cache is a small fast storage device that acts as a staging area for the data objects stored in a larger slower device