Assembly Language Flashcards
What is the Von Neumann Architecture?
Itis archietecture model which is a concept of storing both data and instructions in the same memory space.
What are the main components of the CPU in the von Neumann Architecture?
- Control Unit
- Arithmetic and Logical Unit (ALU)
- Registers (including Program Counter, Instruction Register, Address Register, Accumulator)
What are the roles of the Program Counter, Instruction Register, and Address Register in the CPU?
Program counter - Address of the NEXT Instruction
Instruction register - Instruction CURRENTLY being executed or decoded
Address register - either stores the memory address from which data will be fetched, or the address to which data will sent and stored
Accumulator - SHORT - term, intermediate storage of arithmetic and logic data computations
What is the role of the Accumulator in the CPU?
It serves as short-term, intermediate storage for results of arithmetic and logic computations.
What is a system bus?
It is a set of physical connection which allows communication between the CPU, memory, and input/output devices.
What are the three types of system buses in the von Neumann Architecture, and what do they carry?
- Control Bus - Carries commands from the CPU and returns status signals from the devices
- Data Bus - carries the actual data
- Address bus - carries memory addresses from the processor to other components
What is the role of Memory (RAM) in the von Neumann Architecture?
It stores both data and instructions temporarily while the system is running.
What is the purpose of Input/Output Units in the von Neumann Architecture?
They allow the CPU to communicate with external devices like keyboards, screens, and storage drives.
What does the clock cycle do in the Von Neumann Architecture?
It provides a high/low oscillating signal to synchronize (coordinate) CPU actions.
How does the clock affect CPU performance?
- The number of clock cycles per second determines CPU speed, measured in megahertz (MHz) or gigahertz (GHz).
- The rate of the Fetch/Execute Cycle is controlled by the computer’s clock.
How much time does a 1 GHz clock give between ticks, and what happens during that time?
One nanosecond per tick; the CPU tries to start the Fetch/Execute Cycle in that time.
What is pipelining in computer architecture?
Pipelining is when completing an instruction is handed off to other circuitry, allowing the fetch unit to start the next instruction before the current one finishes.
Why is it not exactly true that 1,000 instructions execute in 1,000 clock ticks?
Because even with pipelining, overlaps and delays mean that instructions aren’t completed perfectly one per tick.
What are the structures in the Harvard Architecture?
- Separate memory for instructions and Data
- Parallelism
What are the purposes of the two structures in the Harvard Architecture?
- There are two memory spaces inline VNA, where one is for instructions and the other one for data
- Instructions and data can be fetched at the same time, leading to faster execution.
What is the MIPS R4000, and how does it differ from the von Neumann architecture?
The MIPS R4000 is a microprocessor without interlocked pipeline stages. It is similar to von Neumann but has separate interfaces for instructions and data, resembling a modified Harvard architecture.
What is the significance of the “modified Harvard architecture” in the MIPS R4000?
It allows separate handling of instructions and data, improving performance by reducing bottlenecks in data processing.
What are the key features of the MIPS R4000 microprocessor?
- First 64-bit architecture.
- Integrated caches (on-chip and off-chip secondary cache).
- Integrated Floating Point Unit (FPU).
What was the performance and technical setup of the MIPS R4000 when it was implemented in 1992?
- Deep pipeline.
- 1.4 million transistors.
- Initially 100 MHz with over 50 MIPS performance.
What makes the MIPS R4000 programming model simple and efficient?
It has a compact set of instructions with a regular format (MIPS III), making it easy to translate high-level code to machine language.
Where is the IF tag check done in the MIPS R4000 pipeline?
The IF tag check is performed in the Register File (RF) stage.
What happens in the IF and IS stages of the MIPS R4000 pipeline?
IF: First half of instruction fetch; PC selection and initiation of instruction cache access.
IS: Second half of instruction fetch; completes instruction cache access.
What occurs during the RF and EX stages in the MIPS R4000 pipeline?
RF: Instruction decode, register fetch, hazard checking, and instruction cache hit detection.
EX: Execution; includes effective address calculation, ALU operations, branch target completion, and data cache access.
Describe the functions of the DF, DS, TC, and WB stages in the MIPS R4000 pipeline.
DF: First half of data cache access.
DS: Second half of data fetch; completes data cache access.
TC: Tag check to determine whether the data cache access hit.
WB: Write-back for loads and register-register operations.
What are the main components of the MIPS R4000 processor?
- Program counter
- Instruction register
- Control unit
- Floating Point Unit (FPU)
How are the registers organized in the MIPS R4000, and what are their key functions?
- 32 x 32-bit/64-bit registers, denoted $0-$31 (or r0-r31).
- $0 (r0): Always stores 000…000.
- $31 (r31): The link register used by Jump and Link instructions (should not be used by other instructions).
How does the Arithmetic and Logic Unit (ALU) in the MIPS R4000 function?
- Takes input from up to two registers.
- Sends output only to registers (except when calculating memory addresses).
What is the typical process for running a program written in a high-level programming language?
High-level languages are compiled into assembly language, which is then assembled into binary code that the computer can execute.
Why are high-level programming languages preferred?
They offer special statement forms that help programmers describe complex tasks more easily.
What do computers actually understand, and what is the machine level?
Computers understand machine-level programs, which are made up of complex combinations of simple instructions
What is an Instruction Set Architecture (ISA)?
An ISA is the unique set of instructions that a particular machine can understand and execute.
What does the instruction set represent to a programmer?
It is the set of operations the CPU can execute — the “tools” a programmer sees and uses to control the machine.
How do high-level and low-level programs differ in terms of instructions?
- High-level programs describe what and how tasks should be done.
- Low-level programs also specify where operations happen (e.g., specific memory addresses or registers).
What form must software be in for a computer to execute it?
Software must be in binary object code (strings of 0’s and 1’s).
What is assembly language, and why is it used?
Assembly language is a human-readable alternative to machine language that uses letters and normal numbers to make programming easier.
How does a computer process assembly code into binary object code?
- Scans the assembly code.
- Looks up words in a table to convert to binary.
- Converts numbers to binary.
- Assembles the binary pieces into complete instructions.
What is MIPS Assembly Language, and who created it?
MIPS is a RISC (Reduced Instruction Set Computer) architecture created by John Hennessy and a team at Stanford University in the early 1980s.
How does “Simplicity Favours Regularity” apply to MIPS instruction formats?
All MIPS instructions are the same length (32 bits) and follow a fixed format with a small number of fields, making decoding easier and hardware design simpler.
How does MIPS maintain consistency in operand usage?
MIPS uses a fixed number of operands—typically two source operands and one destination operand—which speeds up hardware performance and reduces complexity.
What does “Make the Common Case Fast” mean in MIPS architecture?
MIPS optimises frequently used instructions like arithmetic and load/store operations, while complex instructions are broken down into simpler ones.
How does the Load/Store architecture contribute to MIPS efficiency?
In MIPS, all operations (except load and store) occur between registers, with memory access only through LW (load word) and SW (store word) instructions, simplifying execution and speeding up common operations.
How does having a limited number of instructions make MIPS faster?
Using a small, simple instruction set reduces hardware complexity, allowing for faster instruction execution.
Why does MIPS use only 32 general-purpose registers?
32 registers balance performance and simplicity — enough to reduce memory access without making instruction decoding and execution slower.
How does MIPS apply the idea that “Good Design Demands Good Compromises”?
MIPS, as a RISC architecture, prioritizes simple and fast instructions over complex ones, balancing hardware simplicity with software flexibility.
How does pipelining represent a design compromise in MIPS?
Pipelining increases instruction throughput but requires balancing longer pipelines with managing hazards from instruction dependencies.
Why do computers use registers, and how many does MIPS have?
Registers provide fast storage for binary operands because main memory (RAM) is slow. MIPS has 32 fast registers.
How are MIPS registers named, and what is special about register 0?
MIPS registers start with a “$”, e.g., $0 is “register zero” and always holds the constant value 0.
What are the specific uses for the $s and $t registers in MIPS?
- $s0-$s7 are used to store variables.
- $t0-$t9 are used for holding intermediate values.
Why do MIPS registers have limited space for data, and how is this issue handled?
MIPS has only 32 registers, which are small in number. To handle larger data, memory is used, but it’s slower than registers.
What is the best practice for using registers and memory in MIPS?
Frequently used variables are kept in registers, while a combination of registers and memory is used to access large amounts of data quickly.
How does the memory address calculation work with the sw (store word) instruction in MIPS?
The memory address is calculated by adding an offset to the base address stored in a register:
address = base_register + offset.
Can the offset in the sw instruction be written in different formats?
Yes, the offset can be written in either decimal (default) or hexadecimal format.
What are three MIPS instruction types?
- I-type (Immediate)
- R-type (Register)
- J-type (Jump)
What does each MIPs instruction types require?
- Immediate require one or two registers and a value
- Register require three registers
- Jump require a value
What are the three main register operands in an R-type MIPS instruction?
- Source1 and Source2: Source registers
- Dest: Destination register
What other fields are part of the R-type MIPS instruction format?
- Opcode: Operation code (0 for R-type instructions)
- Shift: The shift amount (0 if not a shift instruction)
- Func: The function to be performed (e.g., add, subtract, etc.)
What are the operands in an I-type MIPS instruction?
- Source1 and Dest: Register operands
- Value: A 16-bit immediate value
What is the role of the Opcode in an I-type instruction?
- The Opcode specifies the operation to be performed. Different operations have different Opcodes.
What is the key operand in a J-type MIPS instruction?
The key operand is a 16-bit value, which represents the jump target address.
The key operand is a 16-bit value, which represents the jump target address.
The Opcode specifies the jump operation. Different jump operations have different Opcodes.
