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ARM Flashcards

1
Q

which type of architecture does ARM follow

A

Von Neumann architecture

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2
Q

when was ARM 1 prototype created

A

1985

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3
Q

what type of machine is ARM

A

Advanced RISC machine

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4
Q

what is core data path?

A
  1. data items are placed in register file (no direct manipulation in memory)
  2. two source registers and single result register
  3. a barrel shifter on the data path can preprocess data before it enters ALU
    4, increment/decrement logic can update register content for sequential access independent of ALU
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5
Q

what is CISC design philosophy

A
  1. large instructions set
  2. reduce software complexity by increasing the complexity of processor architecture
  3. very small registers available
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6
Q

What is ARM design philosophy

A
  1. REDUCE POWER CONSUMPTION
  2. High CODE DENSITY
  3. price sensitive
  4. REDUCE AREA OF THE DIE taken up by the embedded processor
  5. INCORPORATED hardware debug technology (ICE)
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7
Q

what is arm core and how is it different from arm processor

A

ARM licenses its core out and other companies make processors based on its cores

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8
Q

What does this mean REDUCE AREA OF THE DIE taken up by the embedded processor

A

die area directly impacts the manufacturing cost, so to keep the cost low, reduced area is better. ARM focuses on designing compact and efficient processors that occupy minimal die area while still delivering optimal performance

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9
Q

What does this mean INCORPORATED hardware debug technology (ICE)

A

hardware debug technology facilitates software development and debugging process, streamline development process

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10
Q

What does high code density mean in ARM design philosophy

A

it tries to fit more instructions in a smaller memory footprint, crucial for devices with limited memory and embedded devices

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11
Q

what does break point and watch point support mean?

A

A breakpoint is a specific point in the program’s code where the execution of the program halts temporarily.

A watchpoint is a debugging feature that monitors the value of a variable or memory location during program execution.

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12
Q

what are the four major design rules of RISC

A
  1. instructions
  2. pipelines
  3. registers
  4. load-store architecture
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13
Q

what are some examples of CISC Design philosophy

A

Intel X86 family,motorola 68000 series

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14
Q

talk about registers

A

32 bits, hold either data or address

user mode: 16 data registers and 2 status registers

r0-r15

r13,r14, r15 0 special functions

r13 stack pointer
r14 link register( where return address is stored when a subroutine is called)
r15 PC

r13 and r14 can also be used as GPR

any instr which uses R0 canas well be used with any other GPR (1-13)

status registersL CPSR: current program status register
SPSR: saved program status register

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15
Q

RISC design philosophy

A
  1. characterized by limited no of instructions
  2. complex instr is obtained by a sequence of simple instructions
  3. software is complex but processor architecture is simple
  4. large no of registers requires
  5. pipelined instruction execution
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16
Q

In ARM7TDMI what does TDMI stand for can you explain eavh point

A

T - Thumb 16 but compressed instruction set
D - Onchip Debug request
M - enhanced Multiplier (yields 64 bit result)
I - Embedded ICE hardware to give on chip breakpoint and watchpoint support

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17
Q

Explain about the load-store architecture

A

load and store instruction transfers data between the register bank and the external memory

memory accesses are costly, slow processor down

separating memory access from data processing provides an advantage

you can use data items held in register banks multiple times without needing multiple memory accesses

addressing mode for every operand is fixed (no bytes for addressing mode info)

for all arithmetic/logical type register mode

load: memory -> register
store: register -> memory

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18
Q

Examples of RICS machines

A

ARM, Atmel AVR, MIPS , Power PC

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19
Q

draw the diagram for ARM core dataflow model

A

check ppt 31 slide 15

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20
Q

can you explain everything about registers in major design rules in RISC

A
  1. large general purpose register set
  2. any register can contain either data or address
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21
Q

can you explain everything about pipelines in major design rules in RISC

A
  1. The processing of instructions can be broken down into snaller units that can be executed in parallel by pipelines
  2. pipeline advances by one step on each cycle for maximum throughput
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22
Q

can you explain everything about instructions in major design rules in RISC

A
  1. reduced number of instructions
  2. execute in a single cycle
  3. compiler synthesizes complicated operations
  4. each instruction is a fixed length
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23
Q

Arms most successful cores and its advantages

A

ARM7TDMI
high code density, low power consumption

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24
Q

ARM is a key component of which devices

A

32-bit embedded systems, portable consumer devices

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25
ARM core dataflow model
1. functional units connected by data bus( data or instruction) 2. von neumann ( data and instr share same bus) 3. register file - 32 bit registers 4. ARM instruction has 2 source and 1 desination register 5. L/S inst: use the ALU to generate an address to be held in the address reg, and broadcasted on the address bus 6. Result bus
26
how many bits are there in each register
32bits
27
what do general purpose registers hold?
Data or Address
28
In user mode how many registers are there
16 data registers 2 status registers
29
which registers perform special function
r13, r14, r15
30
what are the special functions of r13, r14, r15
r13 -stack pointer r14 -link register (where return address is stored whenever a subroutine is called) r15 -program counter
31
among r13, r14 and r15 which two can be used as GPR
r13 and r14
32
what are the two PSR
CPSR - current program status register SPSR - saved program status register
33
Draw program status register and mention each of its sections
34
what are conditional code flags and what do they mean
1. N: negative result from ALU 2. Z: zero result from ALU 3. C: ALU operation carried out 4. V: ALU operation overflowed
35
what does the current mode of the processor determine?
It determines which registers are available to the processor(register which are active and rights to cpsr itself)
36
What are the processor modes?
1. Abort - failed attempt to access memory 2. FIQ 3. IRQ - two interrupt levels available on the arm processor 4. Supervisor - OS kernel operates 5. System - special version of user mode that allows full R/W access to dpsr 6. Undefined - processor encounters an instr that is undefined 7. User- used in programs and applications
37
In which mode does the core start
when power is applied to the core it starts in supervisor mode
38
what types can each processor mode be?
privileged - full read write access to CPSR non privileged - only read write access to control field of the CPSR but read write access to the control flags
39
Of the seven modes in ARM which one is non privileged
user
40
what is user mode used for
program and applications
41
explain about each privileged mode
1 Abort: when there is a failed attempt to access memory 2 Fast Interrupt Request (FIQ) & interrupt request: correspond to interrupt levels available on ARM 3 Supervisor mode: state after reset and generally the mode in which OS kernel executes 4 System mode: special version of user mode that allows full read write access of CPSR 5 Undefined: When processor encounters an undefined instruction
42
how many registers are there in register file?
37
43
what are banked registers
20 registers which are hidden from program at different times(available only in particular mode)
44
how do registers in processor modes work
* Processor modes (other than system mode) have a set of associated banked registers that are subset of 16 registers * Maps one to one onto a user mode register
45
which register is used in each privileged mode except system
SPSR( stored program status register) used to save the state of cpsr when the privileged mode is entered in order that the user state can be fully restored when the user process is resumed
46
how does mode changing occur
writing directly to CPSR hardware when the processor responds to exception or interrupt
47
how do you return to the user mode
special return instruction instructs core to restore the original CPSR and backed registers
48
what happens on changing mode on exception
r13 and r14 - banked replaced with r13-irq, r14-irq spsr_irq stores the previous mode cpsr
49
how do you set processor mode using cpsr?
cpsr is not copied into spsr when a mode change is forced due to a program writing direclty to cpsr abort - 10111 FIQ - 10001 IRQ - 10010 supervisor - 10011 system 11111 undefined 11011 user 10000
50
what are the three instruction sets
ARM THUMB JAZELLE
51
what is Jazelle
closed instruction set and not openly available to take advantage of jazelle both extra software has to be licensed from both ARM limited and Sun microsystems
52
can you draw a table differentiating between ARM and Thumb, 8 points of difference. also mention Jazelle instruction size and core instruction
Instruction size core instruction conditional execution data processing instruction program status register register usage Jazelle : T-0, J=1 instruction size : 8bit core instruction: over 60% of the java bytecode implemented in hardware, rest of the code implemented in software
53
what are interrupt masks
used to stop specific interrupt requests from interrupting the processor I=1 (masks IRQ) F=1 (masks IFQ)
54
what are the condition flags again?
Q (Saturation) result cause overflow V oVerflow result causes SIGNED overflow C carry result causes unsigned carry Z result is zero N bit 31 is binary 1
55
how is a condition specified in ARM
two letter suffix EQ or CC etc The condition is tested against the current processor flags and if not met the instruction is treated as a no-op this feature often removes the need for branching and increase speed, code density
56
write the code for a conditional statement if(r2 != 10) r5 = r5 +10 -r3
CMP r2, #10 ADDNE r5,r5,r2 SUBNE r5,r5,r3
57
what is pipelining in RISC
It is a mechanism RISC processor use to execute instructions Using a pipeline speeds us the execution by fetching the next instructions while other instructions are being decoded and executed
58
what is ARM 7 3 stage pipeline
fetch- loads instr from memory decode- identifies the instr to be executed execute- processes the instr and write the result back to a register
59
what are the five stages of pipeline in ARM9
1. fetch -intr fetched placed in instr pipeline 2. decode -instr decoded and register operands read from the register file 3. execute -operand shifted ALU result generated 4.memory (buffer/data) -data memory is accessed if required.Otherwise ALU result is buffered for one clock cycle to give the same pipeline flow for all instructions 5. write ( write/back) result written back to register file, including any data loaded from memory
60
what will happen if an interrupt has been raised in the execute state?
Instr will still complete
61
what does the execution of branch instruction or branching by direct modification of the PC do?
Causes the ARM core to flush its pipeline
62
what happens when an exception or interrupt occurs?
the processor sets the PC to a specific memory address, within vector table, specific instructions that branch to specific routines designed to handle a particular exception or interrupt when an exception or interrupt occurs the processor suspends normal execution and starts loading instructions from the exception vector table
63
what are the various exceptions and interrupts in ARM
RESET - when power is applied branches to initialization code UNDEF (undefined instr) SWI (software interrupt) PABT(prefetch abort) - attempts to fetch an instruction from an address without correct access permissions DABT(data abort)- attempts to fetch data from an address without correct access permissions Reserved IRQ (interrupt request)- by ext hardware FIQ ( fast interrupt request) - by ext hardware requiring fast response time
64
what is the difference between exception and interrupt
exception - internal CPU event floating point overflow trap (SWI) MMU fault( eg page fault) interrupts- external I/O events I/O device request reset but in arm instr manual the two are mixed together
65
what are the priorities of interrupts
I bit ( 1 for all) F bit ( 1 for reset and FIQ) 1. RESET 2. Data Abort 3. FIQ 4. IRQ 5. Prefetch abort 6. Software interrupt 6. Undefined instr
66
can you draw a diagram which connects arm processor modes and exceptions?
abort- data abort prefetch abort SVC -SWI reset
67
when an exception occurs what does arm switch to?
ARM STATE
68
what does the core automatically do when the mode changes to handle exception
saves CPSR to SPSR PC to LR (link register) sets cpsr to exception mode set PC to adress of exception handler
69
what are the steps that ARM processor takes to handle exception and after leaving the exception handler what does it do?
In slide 57 PPT 31
70
how is ARM memory configured
Little endian Big endian
71
what does little endian mean?
low order - lowest address, high order highest address base address + 0 byte0 base address + 1 byte1 base address + 2 byte2 base address + 3 byte3 eg intel processors
72
what does big endian mean
high order - lower address byte address + 0 byte 3 byte address + 1 byte 2 byte address + 2 byte 1 byte address + 3 byte 0 eg motorola processors (used in MAC)

Microprocessor and Microcontroller (2 decks)

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